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24AA02E/OT

更新时间： 2024-02-29 11:44:50
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
24页 325K
描述
2K I2C Serial EEPROM

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24AA02E/OT 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LSSOP,Reach Compliance Code：compliant
Factory Lead Time：18 weeks风险等级：1.62
最大时钟频率 (fCLK)：0.4 MHzJESD-30 代码：R-PDSO-G5
JESD-609代码：e3长度：2.9 mm
内存密度：2048 bit内存集成电路类型：EEPROM
内存宽度：8湿度敏感等级：1
功能数量：1端子数量：5
字数：256 words字数代码：256
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256X8
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
并行/串行：SERIAL峰值回流温度（摄氏度）：260
筛选级别：TS 16949座面最大高度：1.45 mm
串行总线类型：I2C最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.95 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：1.55 mm最长写入周期时间 (tWC)：5 ms
Base Number Matches：1

24AA02E/OT 数据手册

 浏览型号24AA02E/OT的Datasheet PDF文件第2页浏览型号24AA02E/OT的Datasheet PDF文件第3页浏览型号24AA02E/OT的Datasheet PDF文件第4页浏览型号24AA02E/OT的Datasheet PDF文件第6页浏览型号24AA02E/OT的Datasheet PDF文件第7页浏览型号24AA02E/OT的Datasheet PDF文件第8页 
24AA02/24LC02B  
3.4  
Data Valid (D)  
2.0  
FUNCTIONAL DESCRIPTION  
The state of the data line represents valid data when,  
after a Start condition, the data line is stable for the  
duration of the high period of the clock signal.  
The 24XX02 supports a bidirectional, 2-wire bus and  
data transmission protocol. A device that sends data  
onto the bus is defined as transmitter, while a device  
receiving data is defined as a receiver. The bus has to  
be controlled by a master device which generates the  
serial clock (SCL), controls the bus access and gener-  
ates the Start and Stop conditions, while the 24XX02  
works as slave. Both master and slave can operate as  
transmitter or receiver, but the master device  
determines which mode is activated.  
The data on the line must be changed during the low  
period of the clock signal. There is one clock pulse per  
bit of data.  
Each data transfer is initiated with a Start condition and  
terminated with a Stop condition. The number of data  
bytes transferred between Start and Stop conditions is  
determined by the master device and is, theoretically,  
unlimited (although only the last sixteen will be stored  
when doing a write operation). When an overwrite does  
occur, it will replace data in a first-in first-out (FIFO)  
fashion.  
3.0  
BUS CHARACTERISTICS  
The following bus protocol has been defined:  
• Data transfer may be initiated only when the bus  
is not busy.  
3.5  
Acknowledge  
• During data transfer, the data line must remain  
stable whenever the clock line is high. Changes in  
the data line while the clock line is high will be  
interpreted as a Start or Stop condition.  
Each receiving device, when addressed, is obliged to  
generate an acknowledge after the reception of each  
byte. The master device must generate an extra clock  
pulse which is associated with this Acknowledge bit.  
Accordingly, the following bus conditions have been  
defined (Figure 3-1).  
Note:  
The 24XX02 does not generate any  
Acknowledge bits if an internal  
programming cycle is in progress.  
3.1  
Bus not Busy (A)  
The device that acknowledges has to pull down the  
SDA line during the acknowledge clock pulse in such a  
way that the SDA line is stable low during the high  
period of the acknowledge related clock pulse. Of  
course, setup and hold times must be taken into  
account. During reads, a master must signal an end of  
data to the slave by not generating an Acknowledge bit  
on the last byte that has been clocked out of the slave.  
In this case, the slave (24XX02) will leave the data line  
high to enable the master to generate the Stop  
condition.  
Both data and clock lines remain high.  
3.2  
Start Data Transfer (B)  
A high-to-low transition of the SDA line while the clock  
(SCL) is high determines a Start condition. All  
commands must be preceded by a Start condition.  
3.3  
Stop Data Transfer (C)  
A low-to-high transition of the SDA line while the clock  
(SCL) is high determines a Stop condition. All  
operations must be ended with a Stop condition.  
FIGURE 3-1:  
DATA TRANSFER SEQUENCE ON THE SERIAL BUS  
(A)  
(B)  
(D)  
(D)  
(C) (A)  
SCL  
SDA  
Start  
Condition  
Stop  
Condition  
Address or  
Acknowledge  
Valid  
Data  
Allowed  
to Change  
2003 Microchip Technology Inc.  
DS21709C-page 5  
12345678...24

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