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23S09

更新时间： 2023-12-20 18:46:34

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
9页	473K
描述
3.3V Zero Delay Clock Buffer, Spread Spectrum Compatible

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23S09 数据手册

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IDT23S09

3.3VZERODELAYCLOCKBUFFER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

SWITCHINGCHARACTERISTICS(23S09-1)-INDUSTRIAL^(1,2)

Symbol

Parameter

Conditions

Min.

10

10

40

—

—

—

—

1

Typ.

—

—

50

—

—

—

0

Max.

133

100

60

Unit

t1

OutputFrequency

10pFLoad

30pFLoad

MHz

Duty Cycle = t2 ÷ t1

RiseTime

Measured at 1.4V, FOUT = 66.66MHz

Measured between 0.8V and 2V

Measured between 0.8V and 2V

Alloutputsequallyloaded

%

t3

t4

2.5

ns

ns

ps

ps

ns

ps

ps

FallTime

2.5

t5

OutputtoOutputSkew

250

350

8.7

t6A

t6B

t7

Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2

Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT23S09 only)

5

Device-to-Device Skew

Cycle-to-Cycle Jitter

Measured at VDD/2 on the CLKOUT pins of devices

Measuredat66.66MHz,loadedoutputs

—

—

0

700

200

tJ

—

tLOCK

PLLLockTime

Stable power supply, valid clock presented on REF pin

—

—

1

ms

NOTES:

1. REF Input has a threshold voltage of VDD/2.

2. All parameters specified with loaded outputs.

SWITCHINGCHARACTERISTICS(23S09-1H)-INDUSTRIAL^(1,2)

Symbol

Parameter

Conditions

Min.

10

Typ.

—

Max.

133

Unit

t1

OutputFrequency

10pFLoad

30pFLoad

MHz

10

—

100

Duty Cycle = t2 ÷ t1

Duty Cycle = t2 ÷ t1

RiseTime

Measured at 1.4V, FOUT = 66.66MHz

Measured at 1.4V, FOUT <50MHz

Measured between 0.8V and 2V

Measured between 0.8V and 2V

Alloutputsequallyloaded

40

45

—

—

50

50

—

—

60

55

%

%

ns

ns

t3

t4

1.5

1.5

FallTime

t5

t6A

t6B

t7

OutputtoOutputSkew

—

—

1

—

0

250

350

8.7

ps

ps

ns

ps

Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2

Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT23S09 only)

5

Device-to-Device Skew

OutputSlewRate

Measured at VDD/2 on the CLKOUT pins of devices

Measured between 0.8V and 2V using Test Circuit 2

Measuredat66.66MHz,loadedoutputs

—

0

700

t8

tJ

1

—

—

—

—

200

1

V/ns

ps

Cycle-to-Cycle Jitter

PLLLockTime

—

—

tLOCK

NOTES:

Stable power supply, valid clock presented on REF pin

ms

1. REF Input has a threshold voltage of VDD/2.

2. All parameters specified with loaded outputs.

5

1 2 3 456 7 8 9

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