Datasheet > 2308B-5HPGI8

2308B-5HPGI8

更新时间： 2024-01-12 17:46:17

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
17页	399K
描述
PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, TSSOP-16

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2308B-5HPGI8 数据手册

IDT2308B

3.3 VOLT ZERO DELAY CLOCK MULTIPLIER

CLOCK MULTIPLIER

Pin Assignment

Applications

• SDRAM

• Telecom

• Datacom

• PC Motherboards/Workstations

• Critical Path Delay Designs

Function Table¹Select Input Decoding

S2 S1

CLKA

CLKB

Output PLL Shut

Source

Down

Tri-state Tri-state

PLL

Driven

Tri-state

Driven

PLL

REF

PLL

Note 1: H = HIGH voltage level; L = LOW voltage level

Pin Descriptions

Pin Number

Pin Name

REF¹

CLKA1²

CLKA2²

VDD

Pin Description

Input Reference Clock, 5 Volt Tolerant Input

Clock Output for Bank A

3.3 V Supply

GND

Ground

CLKB1²

CLKB2²

S2³

Clock Output for Bank B

Select Input, Bit 2

S1³

Select Input, Bit 1

CLKB3²

CLKB4²

GND

Clock Output for Bank B

Ground

VDD

3.3 V Supply

CLKA3²

CLKA4²

FBK

Clock Output for Bank A

PLL Feedback Input

Notes:

1. Weak pull-down.

2. Weak pull-down on all outputs.

3. Weak pull-up on these inputs.

IDT™ 3.3 VOLT ZERO DELAY CLOCK MULTIPLIER

IDT2308B

REV B 030509

123 4 5 6 7...17

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