2308-1HDCGI

更新时间： 2024-02-03 16:26:49

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
13页	165K
描述
3.3V ZERO DELAY CLOCK MULTIPLIER

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数据手册

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2308-1HDCGI 数据手册

IDT2308

3.3VZERODELAYCLOCKMULTIPLIER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

PINCONFIGURATION

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

Symbol

Rating

Max.

–0.5to+4.6

–0.5to+5.5

–0.5to

Unit

VDD

SupplyVoltageRange

InputVoltageRange(REF)

InputVoltageRange

(except REF)

(2)

REF

FBK

CLKA1

CLKA4

CLKA3

VDD

VDD+0.5

–50

IIK (VI < 0)

IOK

InputClampCurrent

TerminalVoltagewithRespect

CLKA2

±50

VDD

(VO < 0 or VO > VDD) to GND (inputs VIH 2.5, VIL 2.5)

GND

CLKB1

CLKB2

GND

CLKB4

CLKB3

ContinuousOutputCurrent

±50

(VO = 0 to VDD)

VDD or GND

TA = 55°C

(instillair)⁽³⁾

TSTG

ContinuousCurrent

±100

0.7

MaximumPowerDissipation

StorageTemperatureRange

CommercialTemperature

Range

–65to+150

0 to +70

°C

Operating

Temperature

Operating

Temperature

NOTES:

SOIC/ TSSOP

TOP VIEW

IndustrialTemperature

Range

-40to+85

°C

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

PINDESCRIPTION

2. The input and output negative-voltage ratings may be exceeded if the input and output

clamp-current ratings are observed.

Pin Number

FunctionalDescription

REF ⁽¹⁾

CLKA1⁽²⁾

CLKA2⁽²⁾

VDD

InputReferenceClock,5VoltTolerantInput

Clock Output for Bank A

3.3V Supply

3. The maximum package power dissipation is calculated using a junction temperature

^{of 150}°C and a board trace length of 750 mils.

GND

Ground

CLKB1⁽²⁾

CLKB2⁽²⁾

S2⁽³⁾

Clock Output for Bank B

Select Input, Bit 2

APPLICATIONS:

• SDRAM

• Telecom

S1⁽³⁾

Select Input, Bit 1

• Datacom

• PC Motherboards/Workstations

• Critical Path Delay Designs

CLKB3⁽²⁾

CLKB4⁽²⁾

GND

Clock Output for Bank B

Ground

VDD

3.3V Supply

CLKA3⁽²⁾

CLKA4⁽²⁾

FBK

Clock Output for Bank A

PLLFeedbackInput

NOTES:

1. Weak pull down.

2. Weak pull down on all outputs.

3. Weak pull ups on these inputs.

123 4 5 6 7...13

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