21154 PCI-to-PCI Bridge
Contents
1.0
Introduction.........................................................................................................................1
1.1
1.2
Architecture ...........................................................................................................3
Data Path ..............................................................................................................5
1.2.1 Posted Write Queue.................................................................................6
1.2.2 Delayed Transaction Queue.....................................................................6
1.2.3 Read Data Queue ....................................................................................6
2.0
Signal Pins .........................................................................................................................7
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Primary PCI Bus Interface Signals........................................................................8
Primary PCI Bus Interface 64-Bit Extension Signals..........................................11
Secondary PCI Bus Interface Signals .................................................................12
Secondary PCI Bus Interface 64-Bit Extension Signals......................................14
Secondary Bus Arbitration Signals......................................................................15
General-Purpose I/O Interface Signals ...............................................................15
Clock Signals.......................................................................................................16
Reset Signals ......................................................................................................16
Miscellaneous Signals.........................................................................................17
JTAG Signals ......................................................................................................18
3.0
4.0
Pin Assignment ................................................................................................................19
3.1
3.2
Numeric Pin Assignment.....................................................................................20
Pins Listed in Alphabetic Order...........................................................................25
PCI Bus Operation ...........................................................................................................31
4.1
4.2
Types of Transactions.........................................................................................31
Address Phase....................................................................................................32
4.2.1 Single Address Phase............................................................................32
4.2.2 Dual Address Phase...............................................................................32
Device Select (DEVSEL#) Generation................................................................33
Data Phase..........................................................................................................33
Write Transactions ..............................................................................................33
4.5.1 Posted Write Transactions .....................................................................34
4.5.2 Memory Write and Invalidate Transactions............................................35
4.5.3 Delayed Write Transactions ...................................................................36
4.5.4 Write Transaction Address Boundaries..................................................38
4.5.5 Buffering Multiple Write Transactions.....................................................38
4.5.6 Fast Back-to-Back Write Transactions...................................................39
Read Transactions ..............................................................................................40
4.6.1 Prefetchable Read Transactions............................................................40
4.6.2 Nonprefetchable Read Transactions......................................................40
4.6.3 Read Prefetch Address Boundaries.......................................................41
4.6.4 Delayed Read Requests ........................................................................41
4.6.5 Delayed Read Completion with Target...................................................42
4.6.6 Delayed Read Completion on Initiator Bus ............................................42
Configuration Transaction ...................................................................................46
4.7.1 Type 0 Access to the 21154...................................................................46
4.7.2 Type 1 to Type 0 Translation..................................................................47
4.3
4.4
4.5
4.6
4.7
Datasheet
iii
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