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1N5376B PDF预览

1N5376B

更新时间: 2024-02-15 15:48:16
品牌 Logo 应用领域
KISEMICONDUCTOR 二极管齐纳二极管测试
页数 文件大小 规格书
5页 428K
描述
5 Watt Zener Diode 5.1 to 200 Volts

1N5376B 技术参数

生命周期:Obsolete包装说明:O-PALF-W2
针数:2Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8541.10.00.50
风险等级:5.64Is Samacsys:N
其他特性:FORMED LEAD OPTIONS ARE AVAILABLE外壳连接:ISOLATED
配置:SINGLE二极管元件材料:SILICON
二极管类型:ZENER DIODEJESD-30 代码:O-PALF-W2
元件数量:1端子数量:2
封装主体材料:PLASTIC/EPOXY封装形状:ROUND
封装形式:LONG FORM极性:UNIDIRECTIONAL
最大功率耗散:5 W认证状态:Not Qualified
标称参考电压:87 V最大反向电流:0.5 µA
表面贴装:NO技术:ZENER
端子形式:WIRE端子位置:AXIAL
最大电压容差:5%工作测试电流:15 mA
Base Number Matches:1

1N5376B 数据手册

 浏览型号1N5376B的Datasheet PDF文件第1页浏览型号1N5376B的Datasheet PDF文件第2页浏览型号1N5376B的Datasheet PDF文件第4页浏览型号1N5376B的Datasheet PDF文件第5页 
1N5338B THRU 1N5388B  
3. SURGE CURRENT (Ir) - Surge current is specified as the maximum allowable peak, non-recurrent square-wave  
current with a pulse width, PW, of 8.3 ms. The data given in Figure 5 may be used to find the maximum surge  
current for a quare wave of any pulse width between 1 ms and 1000ms by plotting the applicable points on  
logarithmic paper. Examples of this, using the 6.8v , is shown in Figure 6. Mounting  
ć
contact located as specified in Note 3. (TA=25 ).  
4. VOLTAGE REGULATION (Vz) - Test conditions for voltage regulation are as follows: Vz measurements are made  
at 10% and then at 50% of the Iz max value listed in the electrical characteristics table. The test currents are the  
same for the 5% and 10% tolerance devices. The test current time druation for each Vz measurement is 40+/- 10 ms.  
(TA=25C ). Mounting contact located as specified in Note2.  
5. MAXIMUM REGULATOR CURRENT (IZM) - The maximum current shown is based on the maximum voltage of a  
5% type unit. Therefore, it applies only to the B-suffix device. The actual IZM for any device may not exceed the  
value of 5 watts divided by the actual Vz of the device. TL=75Cat maximum from the device body.  
APPLICATION NOTE:  
Since the actual voltage available from a given Zener  
diode is temperature dependent, it is necessary to determine  
junction temperature under any set of operating conditions  
in order to calculate its value. The following procedure is  
recommended:  
For worst‐case design, using expected limits of I , limits  
Z
of P and the extremes of T (DT ) may be estimated.  
D
J
J
Changes in voltage, V , can then be found from:  
Z
DV = qVZ DTJ  
q
, the Zener voltage temperature coefficient, is found  
VZ  
from Figures 2 and 3.  
Lead Temperature, T , should be determined from:  
L
TL = qLA PD + TA  
Under high power‐pulse operation, the Zener voltage will  
vary with time and may also be affected significantly by the  
zener resistance. For best regulation, keep current  
excursions as low as possible.  
q
power dissipation.  
is the lead‐to‐ambient thermal resistance and P is the  
D
LA  
Junction Temperature, T , may be found from:  
J
TJ = TL + DTJL  
Data of Figure 4 should not be used to compute surge  
capability. Surge limitations are given in Figure 5. They are  
lower than would be expected by considering only junction  
temperature, as current crowding effects cause temperatures  
to be extremely high in small spots resulting in device  
degradation should the limits of Figure 5 be exceeded.  
DT is the increase in junction temperature above the lead  
JL  
temperature and may be found from Figure 4 for a train of  
power pulses or from Figure 1 for dc power.  
DTJL = qJL PD  
KI SEMICONDUCTOR  

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