Integrated Device Technology, Inc.
Document Type: Data Sheet
ICS1893BF
Document Stage: Rev. F Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
General
Features
The ICS1893BF is a low-power, physical-layer device (PHY)
that supports the ISO/IEC 10Base-T and 100Base-TX
Carrier-Sense Multiple Access/Collision Detection
(CSMA/CD) Ethernet standards, ISO/IEC 8802-3.
• Supports category 5 cables with attenuation in excess of
24dB at 100 MHz.
• Single-chip, fully integrated PHY provides PCS, PMA, PMD,
and AUTONEG sub layers functions of IEEE standard.
The ICS1893BF is intended for MII, Node applications that
require the Auto-MDIX feature that automatically corrects
crossover errors in plant wiring.
• 10Base-T and 100Base-TX IEEE 8802.3 compliant
• Single 3.3V power supply
The ICS1893BF incorporates Digital-Signal Processing (DSP)
control in its Physical-Medium Dependent (PMD) sub layer. As
a result, it can transmit and receive data on unshielded
twisted-pair (UTP) category 5 cables with attenuation in
excess of 24 dB at 100MHz. With this ICS-patented
technology, the ICS1893BF can virtually eliminate errors from
killer packets.
• Highly configurable, supports:
– Media Independent Interface (MII)
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M full and half-duplex modes
– Loopback mode for Diagnostic Functions
– Auto-MDI/MDIX crossover correction
The ICS1893BF provides a Serial-Management Interface for
exchanging command and status information with a
Station-Management (STA) entity. The ICS1893BF
Media-Dependent Interface (MDI) can be configured to
provide either half- or full-duplex operation at data rates of 10
Mb/s or 100Mb/s.
• Low-power CMOS (typically 400 mW)
• Power-Down mode typically 21mW
• Clock and crystal supported
• Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
The ICS1893BF is available in a 300-mil 48-lead SSOP
package. The ICS1893BF shares the same proven
performance circuitry with the ICS1893AF but is not a
pin-for-pin replacement of the 1893AF. An application note for
a dual footprint layout to accommodate ICS1893AF or
ICS1893BF is available on the ICS website.
• Small footprint 48-pin 300 mil. SSOP package
• Also available in small footprint 56-pin 8x8 MLF2 package
• Available in Industrial Temp
Applications: NIC cards, PC motherboards, switches,
routers, DSL and cable modems, game machines,
printers.
ICS1893BF Block Diagram
100Base-T
PCS
PMA
TP_PMD
•
•
Framer
CRS/COL
Detection
Parallel to Serial
4B/5B
•
•
•
•
Clock Recovery
Link Monitor
Signal Detection
Error Detection
•
•
•
•
MLT-3
10/100 MII
MAC
Interface
Twisted-
Pair
Interface to
Magnetics
Modulesand
RJ45
Interface
MUX
Integrated
Switch
Stream Cipher
Adaptive Equalizer
Baseline Wander
Correction
•
•
10Base-T
Connector
MII
Low-Jitter
Clock
Synthesizer
Auto-
Negotiation
Configuration
and Status
Extended
Register
Set
MII
Management
Interface
Clock
Power
LEDs and PHY
Address
IDT reserves the right to make changes in the device data identified in
this publication without further notice. IDT advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
ICS1893BF, Rev. F, 5/13/10
May, 2010
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