1339 Datasheet
ESR (Effective Series Resistance)
PCB Layout
Choose the crystal with lower ESR. A low ESR helps the
crystal to start up and stabilize to the correct output
frequency faster compared to high ESR crystals.
Frequency Tolerance
1339
The frequency tolerance for 32kHz crystals should be
specified at nominal temperature (+25°C) on the crystal
manufacturer datasheet. The crystals used with 1339
typically have a frequency tolerance of ±20ppm at +25°C.
Specifications for a typical 32kHz crystal used with our
device are shown in the table below.
PCB Assembly, Soldering and Cleaning
Board-assembly production process and assembly quality
can affect the performance of the 32kHz oscillator.
Depending on the flux material used, the soldering process
can leave critical residues on the PCB surface. High
humidity and fast temperature cycles that cause humidity
condensation on the printed circuit board can create
process residuals. These process residuals cause the
insulation of the sensitive oscillator signal lines towards
each other and neighboring signals on the PCB to decrease.
High humidity can lead to moisture condensation on the
surface of the PCB and, together with process residuals,
reduce the surface resistivity of the board. Flux residuals on
the board can cause leakage current paths, especially in
humid environments. Thorough PCB cleaning is therefore
highly recommended in order to achieve maximum
performance by removing flux residuals from the board after
assembly. In general, reduction of losses in the oscillator
circuit leads to better safety margin and reliability.
Parameter
Nominal Freq.
Symbol Min
Typ
Max Unit
fO
ESR
CL
32.768
kHz
Series Resistance
Load Capacitance
50
k
7
pF
PCB Design Consideration
• Signal traces between Renesas device pins and the
crystal must be kept as short as possible. This minimizes
parasitic capacitance and sensitivity to crosstalk and
EMI. Note that the trace capacitances play a role in the
effective crystal load capacitance calculation.
• Data lines and frequently switching signal lines should be
routed as far away from the crystal connections as
possible. Crosstalk from these signals may disturb the
oscillator signal.
• Reduce the parasitic capacitance between X1 and X2
signals by routing them as far apart as possible.
Power Control
• The oscillation loop current flows between the crystal and
the load capacitors. This signal path (crystal to CL1 to
CL2 to crystal) should be kept as short as possible and
ideally be symmetric. The ground connections for both
capacitors should be as close together as possible.
Never route the ground connection between the
capacitors all around the crystal, because this long
ground trace is sensitive to crosstalk and EMI.
The power-control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the VCC level. The device is
fully accessible and data can be written and read when VCC
is greater than VPF. However, when VCC falls below VPF, the
internal clock registers are blocked from any access. If VPF
is less than VBACKUP, the device power is switched from VCC
to VBACKUP when VCC drops below VPF. If VPF is greater
than VBACKUP, the device power is switched from VCC to
VBACKUP when VCC drops below VBACKUP. The registers are
maintained from the VBACKUP source until VCC is returned to
nominal levels (Table 1). After VCC returns above VPF, read
and write access is allowed after tREC (see the
• To reduce the radiation / coupling from oscillator circuit,
an isolated ground island on the GND layer could be
made. This ground island can be connected at one point
to the GND layer. This helps to keep noise generated by
the oscillator circuit locally on this separated island. The
ground connections for the load capacitors and the
oscillator should be connected to this island.
“Power-Up/Down Timing” diagram).
©2007-2023 Renesas Electronics Corporation
4
April 4, 2023
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