1338 Datasheet
RTC and RAM Address Map
The address map for the RTC and RAM registers shown in Table 3. The RTC registers and control register are located
in address locations 00H to 07H The RAM registers are located in address locations 08H to 3FH. During a multibyte
access, when the register pointer reaches 3FH (the end of RAM space) it wraps around to location 00H (the beginning
of the clock space). On an I2C START, STOP, or register pointer incrementing to location 00H, the current time and date
is transferred to a second set of registers. The time and date in the secondary registers are read in a multibyte data
transfer, while the clock continues to run. This eliminates the need to re-read the registers in case of an update of the
main registers during a read.
Table 3. RTC and RAM Address Map
Address
00H
Bit 7
CH
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
Seconds
Minutes
Range
00 - 59
00 - 59
10 seconds
10 minutes
AM/PM
Seconds
01H
Minutes
Hour
1 - 12
+ AM/PM
00 - 23
02H
0
12/24
10 hour
0
Hours
10 hour
03H
04H
05H
06H
07H
0
0
0
0
0
0
0
0
0
Day
Day
Date
1 - 7
10 date
Date
Month
Year
01 - 31
01 - 12
00 - 99
0
10 month
Month
10 year
Year
OUT
0
OSF
SQWE
0
RS1
RS0
Control
RAM 56 x 8
08H -
3FH
00H - FFH
Note: Bits listed as “0” should always be written and read as 0.
Clock and Calendar
Table 3 shows the address map of the RTC registers. The
time and date information is obtained by reading the
appropriate register bytes. The time and calendar are set
or initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
BCD format. Bit 7 of Register 0 is the clock halt (CH) bit.
When this bit is set to 1, the oscillator is disabled. When
cleared to 0, the oscillator is enabled. The clock can be
halted whenever the timekeeping functions are not
required, which decreases VBAT current.
The countdown chain is reset whenever the seconds
register is written. Write transfers occurs on the
acknowledge pulse from the device. To avoid rollover
issues, once the countdown chain is reset, the remaining
time and date registers must be written within one
second. If enabled, the 1Hz square-wave output
transitions high 500ms after the seconds data transfer,
provided the oscillator is already running.
Note that the initial power-on state of all registers,
unless otherwise specified, is not defined. Therefore,
it is important to enable the oscillator (CH = 0) during
initial configuration.
The day-of-week register increments at midnight. Values
that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2
equals Monday, and so on). Illogical time and date entries
result in undefined operation.
The IDT1338 runs in either 12-hour or 24-hour mode. Bit
6 of the hours register is defined as the 12-hour or
24-hour mode-select bit. When high, the 12-hour mode is
selected. In the 12-hour mode, bit 5 is the AM/PM bit,
with logic high being PM. In the 24-hour mode, bit 5 is the
second 10-hour bit (20–23 hours). If the 12/24-hour mode
select is changed, the hours register must be
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any start or stop, and when the
address pointer rolls over to zero.
re-initialized to the new format.
©2008–2023 Renesas Electronics Corporation
6
February 3, 2023
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