Datasheet > 11257-806

11257-806

更新时间： 2024-01-02 21:16:54

品牌	Logo	应用领域
其他 - ETC		时钟
页数	文件大小	规格书
19页	384K
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LOW-SKEW CLOCK FANOUT BUFFER ICs

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11257-806 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	28
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.66	Is Samacsys：	N
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G28
长度：	10.2 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	28	实输出次数：	10
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	传播延迟（tpd）：	5 ns
认证状态：	Not Qualified	座面最大高度：	2 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	5.3 mm	Base Number Matches：	1

11257-806 数据手册

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April 1999

4.1.4 Data Valid

4.0 Dual Serial Interface Control

The state of the SDA line represents valid data if the SDA

This integrated circuit is a read/write slave device that

supports both the Inter IC Bus (I²C-bus) and the System

Management Bus (SMBus) two-wire serial interface pro-

tocols. The unique device address that is written to the

device determines whether the part expects to receive

SMBus commands or I²C commands. Since SMBus is

derived from the I²C-bus, the protocol for both bus types

is very similar.

line is stable for the duration of the high period of the SCL

line after a START condition occurs. The data on the

SDA line must be changed only during the low period of

the SCL signal. There is one clock pulse per data bit.

Each data transfer is initiated by a START condition and

terminated with a STOP condition. The number of data

bytes transferred between START and STOP conditions

is determined by the master device, and can continue

indefinitely. However, data that is overwritten to the de-

vice after the data registers are filled will overflow from

the last register into the first register, then the second,

and so on, in a first-in, first-overwritten fashion.

In general, the bus has to be controlled by a master de-

vice that generates the serial clock SCL, controls bus

access, and generates the START and STOP conditions

while the device works as a slave. Both master and slave

can operate as a transmitter or receiver, but the master

device determines which mode is activated. A device that

sends data onto the bus is defined as the transmitter, and

a device receiving data as the receiver.

4.1.5 Acknowledge

When addressed, the receiving device is required to gen-

erate an Acknowledge after each byte is received. The

master device must generate an extra clock pulse to co-

incide with the Acknowledge bit. The acknowledging de-

vice must pull the SDA line low during the high period of

the master acknowledge clock pulse. Setup and hold

times must be taken into account.

Bus logic levels and timing parameters noted herein fol-

low I²C-bus convention. Logic levels are based on a per-

centage of VDD. A logic-one corresponds to a nominal

voltage of VDD, while a logic-zero corresponds to ground

(VSS).

The master must signal an end of data to the slave by not

generating an acknowledge bit on the last byte that has

been read (clocked) out of the slave. In this case, the

slave must leave the SDA line high to allow the master to

generate a STOP condition.

4.1

Bus Conditions

Data transfer on the bus can only be initiated when the

bus is not busy. During the data transfer, the data line

(SDA) must remain stable whenever the clock line (SCL)

is high. Changes in the data line when the clock line is

high is interpreted by the device as a START or STOP

condition. Both I²C-bus and SMBus protocols define the

following conditions on the bus. Refer to Figure 12: Bus

Timing Data for more information.

4.2

Bus Operation and Commands

All programmable registers can be accessed via the bi-

directional two wire digital interface. The device accepts

the Random Register Read/Write and the Sequential

supports the Block Read/Write SMBus commands.

4.1.1 Not Busy

Both the data (SDA) and clock (SCL) lines remain high to

indicate the bus is not busy.

4.2.1 I²C-bus and SMBus Device Addressing

After generating a START condition, the bus master

broadcasts a seven-bit device address followed by a R/W

bit. Note that every device on an I²C-bus or SMBus must

have a unique address to avoid bus conflicts.

4.1.2 START Data Transfer

A high to low transition of the SDA line while the SCL in-

put is high indicates a START condition. All commands to

the device must be preceded by a START condition.

For an SMBus interface, the address of the device is:

4.1.3 STOP Data Transfer

A low to high transition of the SDA line while SCL is held

high indicates a STOP condition. All commands to the

device must be followed by a STOP condition.

4.5.99

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中文翻译

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与11257-806相关器件

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11257-811	ETC	获取价格	LOW-SKEW CLOCK FANOUT BUFFER ICs
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11257-813	ETC	获取价格	LOW-SKEW CLOCK FANOUT BUFFER ICs
11257-814	ETC	获取价格	LOW-SKEW CLOCK FANOUT BUFFER ICs
11257-816	ETC	获取价格	LOW-SKEW CLOCK FANOUT BUFFER ICs
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112589	AMPHENOL	获取价格	RF BNC Connector, Male, Cable Mount, Crimp Terminal, Plug
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