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Series termination adds no dc loading to the driver, and pacitance, and the number of connected devices with
requires less power than other resistive termination their associated input currents.
methods. Further, no extra impedance exists from the
signal line to a reference voltage, such as ground.
Control of the clock and data lines is done through open
drain/collector current-sink outputs, and thus requires
As shown in Figure 19, the sum of the driver’s output im- external pull-up resistors on both lines. A guideline is
pedance (zO) and the series termination resistance (RS)
must equal the line impedance (zL). That is,
tr
RP <
,
2×Cbus
RS = zL − zO
.
where tr is the maximum rise time (minus some margin)
and Cbus is the total bus capacitance. Assuming an I2C
device on each DIMM, an I2C controller, the clock buffer,
and two other bus devices results in values in the 5kΩ to
7kΩ range. Use of a series resistor to provide protection
against high voltage spikes on the bus will alter the val-
ues for RP.
Note that when the source impedance (zO+RS) is
matched to the line impedance, then by voltage division
the incident wave amplitude is one-half of the full signal
amplitude.
(zO + RS )
V
Vi = V
=
(zO + RS ) + zL
2
The full signal amplitude may take up to twice as long as
the propagation delay of the line to develop, reducing
noise immunity during the half-amplitude period. Note
also that the voltage at the receive end must add up to a
signal amplitude that meets the receiver switching
thresholds. The slew rate of the signal is also reduced
due to the additional RC delay of the load capacitance
and the line impedance. Also note that the output driver
impedance will vary slightly with the output logic state
(high or low).
Figure 20: Connections to the Serial Bus
RP
RP
SDA
SCL
RS
(optional)
RS
(optional)
RS
(optional)
RS
(optional)
Data In
Data In
Clock Out
Clock In
Data Out
Data Out
8.2
Dynamic Power Dissipation
TRANSMITTER
RECEIVER
High-speed clock drivers require careful attention to
power dissipation. Transient power (PT) consumption can
be derived from
8.3.1 For More Information
P = VDD 2 ×Cload × fCLK × NSW
More detailed information on serial bus design can be
obtained from SMBus and I2C Bus Design, available from
the Intel Corporation at http://www.intel.com.
Information on the I2C-bus can be found in the document
The I2C-bus And How To Use It (Including Specifica-
tions), available from Philips Semiconductors at
http://www-us2.semiconductors.philips.com.
T
where Cload is the load capacitance, VDD is the supply
voltage, fCLK is the clock frequency, and Nsw is the
number of switching outputs.
The internal heat (junction temperature, TJ) generated by
the power dissipation can be calculated from
Additional information on the System Management Bus
can be found in the System Management Bus Specifica-
tion, available from the Smart Battery System
Implementers’ Forum at http://www.sbs-forum.org.
TJ = ΘJA × P +TA
T
where ΘJA is the package thermal resistance, TA is the
ambient temperature, and PT is derived above.
8.3
Serial Communications
Connection of devices to a standard-mode implementa-
tion of either the I2C-bus or the SMBus is similar to that
shown in Figure 20. Selection of the pull-up resistors (RP)
and the optional series resistors (RS) on the SDA and
SCL lines depends on the supply voltage, the bus ca-
4.5.99
19
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