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10M50SAE144I7G PDF预览

10M50SAE144I7G

更新时间: 2024-02-09 01:43:19
品牌 Logo 应用领域
英特尔 - INTEL 时钟可编程逻辑
页数 文件大小 规格书
14页 604K
描述
Field Programmable Gate Array, PQFP144, 22 X 22 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, EQFP-144

10M50SAE144I7G 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HLFQFP, QFP144,.87SQ,20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:1.52
Samacsys Description:FPGA - Field Programmable Gate Array其他特性:OPERATES AT 3.3V NOMINAL VCC
最大时钟频率:416 MHzJESD-30 代码:S-PQFP-G144
长度:20 mm湿度敏感等级:3
可配置逻辑块数量:3125输入次数:101
逻辑单元数量:50000输出次数:101
端子数量:144最高工作温度:100 °C
最低工作温度:-40 °C组织:3125, CLBS
封装主体材料:PLASTIC/EPOXY封装代码:HLFQFP
封装等效代码:QFP144,.87SQ,20封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY座面最大高度:1.65 mm
最大供电电压:3.15 V最小供电电压:2.85 V
标称供电电压:3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:20 mm
Base Number Matches:1

10M50SAE144I7G 数据手册

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M10-OVERVIEW  
2014.09.22  
3
Summary of MAX 10 Device Features  
Description  
Feature  
Embedded  
multiplier  
blocks  
Support for one 18 x 18 or two 9 x 9 multiplier modes  
Cascadable blocks enabling creation of filters, arithmetic  
functions, and image processing pipelines  
ADC  
12-bits successive approximation register (SAR) type  
Up to 17 analog inputs  
Cumulative speed up to 1 million samples per second ( MSPS)  
Integrated temperature sensing capability  
Embedded hard IP  
Flash memory Support for dual-boot self-configuration technology  
IP  
Clock networks  
Support for global clocks  
High speed frequency in clock network  
Internal Oscillator  
PLLs  
Built-in internal ring oscillator  
Analog-based  
Low jitter  
High precision clock synthesis  
Clock delay compensation  
Zero delay buffering  
Multiple output taps  
General-purpose I/Os (GPIOs)  
External memory interface  
Support multiple I/O standards  
On-chip termination (OCT)  
Up to 830 megabits per second (Mbps) LVDS receiver,  
800 Mbps LVDS transmitter  
Supports up to 600 Mbps external memory interfaces:  
DDR3, DDR3L, DDR2, LPDDR2 (Only for 10M16, 10M25,  
10M40, and 10M50).  
SRAM (Hardware support only. Use your own design to  
interface with SRAM devices.)  
Configuration  
Internal configuration  
JTAG  
Advanced Encryption Standard (AES) 128-bit encryption and  
compression options  
Flash memory data retention of 10 years  
Flexible power supply schemes  
Single and dual supply device options  
Dynamically controlled input buffer power down  
Sleep mode for dynamic power reduction  
MAX 10 FPGA Device Overview  
Send Feedback  
Altera Corporation  

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