TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS649A – DECEMBER 1994 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’124BBK32F-60 ’124BBK32F-70 ’124BBK32F-80
’248CBK32F-60 ’248CBK32F-70 ’248CBK32F-80
UNIT
MIN
10
10
10
5
MAX
MIN
15
10
10
5
MAX
MIN
15
10
10
5
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, W low after CAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
WCH
WRH
CHR
CRP
CSH
CSR
RAD
RAL
CAL
RCD
RPC
RSH
REF
T
Hold time, W high after RAS low (CBR refresh only)
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
Delay time, RAS low to CAS high
60
5
70
5
80
5
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 10)
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 10)
Delay time, RAS high to CAS low (CBR only)
Delay time, CAS low to RAS high
15
30
30
20
0
30
45
15
35
35
20
0
35
52
15
40
40
20
0
40
60
15
18
20
Refresh time interval
16
30
16
30
16
30
Transition time
3
3
3
NOTE 10: The maximum value is specified only to assure access time.
device symbolization (TM124BBK32F illustrated)
TM124BBK32F
-SS
YYMMT
YY = Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed Code
NOTE: Location of symbolization may vary.
7
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