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101X14W470MV4ERC PDF预览

101X14W470MV4ERC

更新时间: 2023-02-15 00:00:00
品牌 Logo 应用领域
约翰逊 - JOHANSON /
页数 文件大小 规格书
6页 430K
描述
Ceramic Capacitor, Multilayer, Ceramic, 100V, 20% +Tol, 20% -Tol, X7R, -/+15ppm/Cel TC, 0.000047uF, 0604,

101X14W470MV4ERC 数据手册

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®
X2Y Filter & Decoupling  
capacitors  
solder  
pAd  
recoMMendAtions  
0402 (X07)  
IN mm  
0603 (X14)  
0805 (X15)  
1206 (X18)  
1210 (X41)  
1410 (X44)  
1812 (X43)  
IN  
mm  
IN  
mm  
1.27  
0.89  
1.27  
0.56  
2.03  
3.05  
IN  
mm  
1.65  
1.02  
2.03  
1.02  
3.05  
4.06  
IN  
mm  
IN  
mm  
IN  
mm  
X
Y
G
V
0.020  
0.020  
0.024  
0.015  
0.039  
0.064  
0.51  
0.51  
0.61  
0.38  
0.99  
1.63  
0.035  
0.025  
0.040  
0.020  
0.060  
0.090  
0.89  
0.64  
1.02  
0.51  
1.52  
2.29  
0.050  
0.035  
0.050  
0.022  
0.080  
0.120  
0.065  
0.040  
0.080  
0.040  
0.120  
0.160  
0.100  
0.040  
0.080  
0.045  
0.160  
0.160  
2.54  
1.02  
2.03  
1.14  
4.06  
4.06  
0.100  
0.040  
0.100  
0.045  
0.160  
0.180  
2.54  
1.02  
2.54  
1.14  
4.06  
4.57  
0.125  
0.040  
0.130  
0.045  
0.190  
0.210  
3.18  
1.02  
3.30  
1.14  
4.83  
5.33  
U
Z
Use of solder mask beneath component is not recommended.  
Z
Z
U
U
X
X
V
V
V
V
Y
G
Y
G
Good Layout  
Poor Layout  
Figure 1  
optiMizing X2Y perForMAnce witH  
proper  
AttAcHMent  
tecHniques  
XꢀY® capacitors excel in low inductance performance for a myriad of applications including EMI/RFI filtering, power supply bypass  
/ decoupling. How the capacitor is attached to the application PCB is every bit as important as the capacitor itself. Proper attention  
to pad layout and via placement insures superior device performance. Poor PCB layouts squander performance, requiring more  
capacitors, and more vias to do the same job. Figure 1 compares the XꢀY® recommended layout against a poor layout. Because  
of its long extents from device terminals to vias, and the wide via separation, the poor layout shown performs badly. It exhibits  
approximately ꢀ00% L1 inductance, and 150% Lꢀ inductance compared to recommended XꢀY layouts.  
For further details on via placement and it’s effect on mounted inductance, please refer to XꢀY Attenuators, LLC. application note  
“Get the Most from XꢀY Capacitors with Proper Attachment Techniques” at www.xꢀy.com/bypass.htm  
®
XꢀY technology patents and registered trademark under license from XꢀY ATTENUATORS, LLC  
Johanson Dielectrics, Inc. reserves the right to make design and price changes without notice. All sales are subject to the terms  
and conditions printed on the back side of our sales order acknowledgment forms, including a limited warranty and remedies for  
non-conforming goods or defective goods. We will be pleased to provide a copy of these terms and conditions for your review.  
JOꢀANSON ꢀONG KONG LTD.  
JOꢀANSON EUROPE LTD.  
Unit E, 11/F., Phase 1, Kaiser Estate  
ꢁ1 Man Yue Street  
Hunghom, Kowloon, Hong Kong  
Tel: (85ꢀ) ꢀ33ꢁ 6310 • Fax: (85ꢀ) ꢀ33ꢁ 8858  
Acorn House, Old Kiln Road  
Flackwell Heath, Bucks HP10 9NR  
United Kingdom  
15191 Bledsoe Street  
Sylmar, California 913ꢁꢀ  
Tel (818) 36ꢁ-9800 • FAX (818) 36ꢁ-6100  
http://www.johansondielectrics.com  
Tel +ꢁꢁ-16ꢀ-853-115ꢁ • Fax +ꢁꢁ-16ꢀ-853-ꢀ703  
© ꢀ007 Publication XꢀY070ꢁ Printed in USA  

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