XRD9814B

更新时间： 2024-02-19 14:51:28

品牌	Logo	应用领域
艾科嘉 - EXAR		传感器
页数	文件大小	规格书
53页	765K
描述
3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors

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技术参数
数据手册

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XRD9814B 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	QFP, TQFP48,.35SQ	Reach Compliance Code：	compliant
风险等级：	5.58	最大模拟输入电压：	5.5 V
转换器类型：	D/A CONVERTER	JESD-30 代码：	S-PQFP-G48
JESD-609代码：	e3	模拟输入通道数量：	3
位数：	14	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	TQFP48,.35SQ	封装形状：	SQUARE
封装形式：	FLATPACK	电源：	5 V
认证状态：	Not Qualified	子类别：	Other Converters
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
Base Number Matches：	1

XRD9814B 数据手册

XRD9814B/9816B

PIN DESCRIPTION - XRD9814B (CONT'D)

Pin No.

Name

Description

RED(-)

N/C

GRN(+)

GRN(-)

N/C

BLU(+)

BLU(-)

N/C

TEST1

TEST2

CREF

CAPP

CAPN

SGND

AGND1

AV_DD1

LCLMP

VSAMP

BSAMP

ADCCLK

INSEL

OUTSEL

OEB

Red Negative Analog Input

No Connect, (Note 5)

Green Positive Analog Input

Green Negative Analog Input

No Connect, (Note 5)

Blue Positive Analog Input

Blue Negative Analog Input

No Connect, (Note 5)

Internal Use Only

Decoupling Cap for CDS Reference

Decoupling Cap for Positive Reference

Decoupling Cap for Negative Reference

Substrate Gnd

Analog Ground (Substrate)

Analog Power Supply

Line Clamp Enable

Video Level Sampling Clock

Black Level Sampling Clock

A/D Converter Clock

Input Mode Select (Note 1)

Output Mode Select (Note 2)

Data Output Enable

Serial Data Input (Note 4)

Serial Shift Clock (Note 3)

Ground (Output Drivers and Internal Decode Logic)

Digital Power Supply (Output Drivers and Internal Decode Logic)

Data I/O Bit 13 (Note 4)

LOAD

SDI

SCLK

DGND

DV_DD

DB13

DB12

DB11

DB10

Data I/O Bit 12 (Note 3)

Data Output Bit 11

Data Output Bit 10

Data Output Bit 9

DB9

Note 1: INSEL=0 —> SCLK, SDI, and LOAD pins are active for serial programming; INSEL=1 —> SCLK and SDI pins

are inactive, and the serial programming is done through I/O pins DB12 and DB13 as described in Notes 3~4 with

LOAD tri-stating DB12 and DB13.

Note 2: OUTSEL=0 —> 14-bit parallel output mode select; OUTSEL=1 —> 8-bit nibble output mode select.

Note 3: For INSEL=1, DB12 becomes the SCLK input during serial programming.

Note 4: For INSEL=1, DB13 becomes the SDI input during serial programming.

Note 5: Pins 17, 20 and 23 may be connected to AGND2 to improve noise immunity.

Rev. 1.00

1 2 345 6 7...53

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