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X4285V8Z-2.7A PDF预览

X4285V8Z-2.7A

更新时间: 2024-02-19 14:43:17
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管
页数 文件大小 规格书
22页 341K
描述
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, 4.40 MM, ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-8

X4285V8Z-2.7A 数据手册

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X4283, X4285  
PRINCIPLES OF OPERATION  
Power-on Reset  
WATCHDOG TIMER  
The Watchdog Timer circuit monitors the microproces-  
sor activity by monitoring the SDA and SCL pins. The  
microprocessor must toggle the SDA pin HIGH to  
LOW periodically, while SCL is HIGH (this is a start bit)  
prior to the expiration of the watchdog time out period to  
prevent a RESET/RESET signal. The state of two non-  
volatile control bits in the Status Register determine  
the watchdog timer period. The microprocessor can  
change these watchdog bits, or they may be “locked”  
by tying the WP pin HIGH.  
Application of power to the X4283, X4285 activates a  
Power-on Reset Circuit that pulls the RESET/RESET  
pin active. This signal provides several benefits.  
– It prevents the system microprocessor from starting  
to operate with insufficient voltage.  
– It prevents the processor from operating prior to sta-  
bilization of the oscillator.  
– It allows time for an FPGA to download its configura-  
tion prior to initialization of the circuit.  
EEPROM INADVERTENT WRITE PROTECTION  
– It prevents communication to the EEPROM, greatly  
reducing the likelihood of data corruption on power-  
up.  
When RESET/RESET goes active as a result of a low  
voltage condition or Watchdog Timer Time-Out, any  
in-progress communications are terminated. While  
RESET/RESET is active, no new communications are  
allowed and no nonvolatile write operation can start.  
Non-volatile writes in-progress when RESET/RESET  
goes active are allowed to finish.  
When V  
exceeds the device V  
threshold value  
CC  
TRIP  
for  
200ms  
(nominal)  
the  
circuit  
releases  
RESET/RESET allowing the system to begin opera-  
tion.  
Additional protection mechanisms are provided with  
memory Block Lock and the Write Protect (WP) pin.  
These are discussed elsewhere in this document.  
LOW VOLTAGE MONITORING  
During operation, the X4283, X4285 monitors the V  
CC  
level and asserts RESET/RESET if supply voltage falls  
below a preset minimum V . The RESET/RESET  
V
THRESHOLD RESET PROCEDURE  
CC  
TRIP  
signal prevents the microprocessor from operating in a  
power fail or brownout condition. The RESET/RESET  
signal remains active until the voltage drops below 1V.  
The X4283, X4285 is shipped with a standard V  
CC  
threshold (V  
) voltage. This value will not change  
TRIP  
over normal operating and storage conditions. How-  
ever, in applications where the standard V is not  
It also remains active until V  
returns and exceeds  
CC  
TRIP  
V
for 200ms.  
TRIP  
exactly right, or if higher precision is needed in the  
value, the X4283, X4285 threshold may be  
V
TRIP  
adjusted. The procedure is described below, and uses  
the application of a nonvolatile control signal.  
Figure 1. Set V  
Level Sequence (V = desired V values WEL bit set)  
TRIP  
TRIP  
CC  
VP = 12-15V  
WP  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
SCL  
SDA  
A0h  
00h  
01h  
00h  
FN8121.1  
May 23, 2006  
5

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