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X28C256EM-15 PDF预览

X28C256EM-15

更新时间： 2023-04-15 00:00:00
品牌 Logo 应用领域
XICOR 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
24页 548K
描述
EEPROM, 32KX8, 150ns, Parallel, CMOS, CQCC32, CERAMIC, LCC-32

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X28C256EM-15 数据手册

 浏览型号X28C256EM-15的Datasheet PDF文件第2页浏览型号X28C256EM-15的Datasheet PDF文件第3页浏览型号X28C256EM-15的Datasheet PDF文件第4页浏览型号X28C256EM-15的Datasheet PDF文件第5页浏览型号X28C256EM-15的Datasheet PDF文件第6页浏览型号X28C256EM-15的Datasheet PDF文件第7页 
256K  
X28C256  
32K x 8 Bit  
5 Volt, Byte Alterable E2PROM  
FEATURES  
DESCRIPTION  
2
• Access Time: 150ns  
• Simple Byte and Page Write  
— Single 5V Supply  
—No External High Voltages or V Control  
Circuits  
— Self-Timed  
The X28C256 is an 32K x 8 E PROM, fabricated with  
Xicor’s proprietary, high performance, floating gate  
CMOS technology. Like all Xicor programmable non-  
volatile memories the X28C256 is a 5V only device. The  
X28C256 features the JEDEC approved pinout for byte-  
widememories,compatiblewithindustrystandardRAMs.  
PP  
—No Erase Before Write  
—No Complex Programming Algorithms  
—No Overerase Problem  
• Low Power CMOS:  
The X28C256 supports a 64-byte page write operation,  
effectively providing a 78µs/byte write cycle and en-  
abling the entire memory to be typically written in less  
than 2.5 seconds. The X28C256 also features DATA  
and Toggle Bit Polling, a system software support  
scheme used to indicate the early completion of a write  
cycle. In addition, the X28C256 includes a user-optional  
software data protection mode that further enhances  
Xicor’s hardware write protect capability.  
—Active: 60mA  
—Standby: 200µA  
• Software Data Protection  
— Protects Data Against System Level  
Inadvertent Writes  
• High Speed Page Write Capability  
™
• Highly Reliable Direct Write Cell  
2
Xicor E PROMs are designed and tested for applica-  
— Endurance: 100,000 Write Cycles  
— Data Retention: 100 Years  
• Early End of Write Detection  
— DATA Polling  
tions requiring extended endurance. Inherent data re-  
tention is greater than 100 years.  
—Toggle Bit Polling  
PIN CONFIGURATION  
LCC  
PLCC  
PLASTIC DIP  
CERDIP  
FLAT PACK  
SOIC  
TSOP  
A
A
A
I/O  
I/O  
I/O  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A
A
A
A
A
A
A
NC  
V
NC  
2
1
0
0
1
2
3
4
5
6
7
12  
14  
A14  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
4
3
2
1
32 31 30  
A
2
WE  
12  
A
A
A
A
A
A
A
5
6
7
8
9
29  
28  
27  
26  
25  
24  
23  
22  
21  
A
A
A
6
5
4
3
2
1
0
8
A
3
A
7
13  
9
A
6
4
A
8
NC  
11  
A
5
A
9
A
5
V
SS  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
OE  
A
X28C256  
A
4
6
9
11  
X28C256  
CC  
10  
11  
12  
13  
14  
15  
16  
A
7
OE  
3
4
5
6
7
3
X28C256  
WE  
10  
11  
12  
13  
10  
A
2
8
A
10  
A
A
A
A
13  
8
9
CE  
I/O  
A
9
CE  
1
NC  
7
A
0
10  
11  
12  
13  
14  
I/O  
7
I/O  
CE  
11  
I/O  
I/O  
0
6
A
I/O  
OE  
10  
0
6
14 15 16 17 18 19 20  
I/O  
1
I/O  
5
I/0  
I/O  
3855 ILL F23  
2
4
V
I/O  
3
SS  
3855 FHD F03  
3855 FHD F02  
© Xicor, Inc. 1991, 1995 Patents Pending  
3855-2.0 8/19/98 T3/C0/D0 RZ  
Characteristics subject to change without notice  
1
1234567...24

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