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X24128S14I-1.8 PDF预览

X24128S14I-1.8

更新时间: 2024-01-29 08:10:13
品牌 Logo 应用领域
XICOR 内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
17页 89K
描述
400KHz 2-Wire Serial E2PROM with Block Lock

X24128S14I-1.8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, SOIC-14Reach Compliance Code:unknown
风险等级:5.91其他特性:100000 ENDURANCE CYCLES; 100 YEARS DATA RETENTION
最大时钟频率 (fCLK):0.4 MHz数据保留时间-最小值:100
耐久性:100000 Write/Erase CyclesI2C控制字节:1010DDDR
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm内存密度:131072 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:14
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:16KX8
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:SERIAL电源:2/3.3 V
认证状态:Not Qualified座面最大高度:1.75 mm
串行总线类型:I2C最大待机电流:0.000001 A
子类别:EEPROMs最大压摆率:0.003 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mm最长写入周期时间 (tWC):10 ms
写保护:HARDWARE/SOFTWAREBase Number Matches:1

X24128S14I-1.8 数据手册

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128K  
16K x 8 Bit  
X24128  
400KHz 2-Wire Serial E2PROM with Block LockTM  
FEATURES  
DESCRIPTION  
2
Save Critical Data with Programmable  
Block Lock Protection  
—Block Lock (0, 1/4, 1/2, or all of E PROM Array)  
The X24128 is a CMOS Serial E PROM, internally  
organized 16K x 8. The device features a serial inter-  
face and software protocol allowing operation on a  
simple two wire bus.  
2
—Software Write Protection  
—Programmable Hardware Write Protect  
In Circuit Programmable ROM Mode  
400KHz 2-Wire Serial Interface  
—Schmitt Trigger Input Noise Suppression  
—Output Slope Control for Ground Bounce  
Noise Elimination  
Longer Battery Life With Lower Power  
—Active Read Current Less Than 1mA  
—Active Write Current Less Than 3mA  
—Standby Current Less Than 1µA  
1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V  
Power Supply Versions  
Three device select inputs (S –S ) allow up to eight  
devices to share a common two wire bus.  
0
2
A Write Protect Register at the highest address loca-  
tion, FFFFh, provides three write protection features:  
Software Write Protect, Block Lock Protect, and  
Programmable Hardware Write Protect. The Software  
Write Protect feature prevents any nonvolatile writes to  
the device until the WEL bit in the Write Protect  
Register is set. The Block Lock Protection feature  
gives the user four array block protect options, set by  
programming two bits in the Write Protect Register.  
The Programmable Hardware Write Protect feature  
allows the user to install the device with WP tied to  
32 Word Page Write Mode  
—Minimizes Total Write Time Per Word  
Internally Organized 16K x 8  
Bidirectional Data Transfer Protocol  
Self-Timed Write Cycle  
V
, write to and Block Lock the desired portions of  
CC  
the memory array in circuit, and then enable the In  
Circuit Programmable ROM Mode by programming the  
WPEN bit HIGH in the Write Protect Register. After  
this, the Block Locked portions of the array, including  
the Write Protect Register itself, are permanently  
protected from being erased.  
—Typical Write Cycle Time of 5ms  
High Reliability  
—Endurance: 100,000 Cycles  
—Data Retention: 100Years  
14-Lead SOIC  
16-Lead SOIC  
8-Lead PDIP  
FUNCTIONAL DIAGRAM  
DATA REGISTER  
Y DECODE LOGIC  
SERIAL E2PROM DATA  
AND ADDRESS (SDA)  
COMMAND  
DECODE  
AND  
CONTROL  
LOGIC  
SERIAL E2PROM  
SCL  
ARRAY  
PAGE  
16K x 8  
DECODE  
LOGIC  
4K x 8  
BLOCK LOCK AND  
WRITE PROTECT  
CONTROL LOGIC  
4K x 8  
8K x 8  
S2  
DEVICE  
SELECT  
LOGIC  
WRITE  
PROTECT  
REGISTER  
S1  
S0  
WRITE VOLTAGE  
CONTROL  
WP  
7027 FM 01  
Xicor, 1995, 1996 Patents Pending  
7027-1.3 5/14/97 T2/C0/D2 SH  
Characteristics subject to change without notice  
1

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