Datasheet > X17256256DD8M

X17256256DD8M

更新时间： 2022-11-25 17:40:29

品牌	Logo	应用领域
赛灵思 - XILINX		可编程只读存储器
页数	文件大小	规格书
10页	103K
描述
QPRO Family of XC1700D QML Configuration PROMs

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

X17256256DD8M 数据手册

QPRO Family of XC1700D QML Configuration PROMs

ation, this pin must be connected to V . Failure to do so

may lead to unpredictable, temperature-dependent opera-

tion and severe problems in circuit debugging. Do not leave

Pin Description

DATA

floating!

Data output, 3-stated when either CE or OE are inactive.

During programming, the DATA pin is I/O. Note that OE can

be programmed to be either active High or active Low.

V_CCand GND

is positive supply pin and GND is ground pin.

CLK

PROM Pinouts

Each rising edge on the CLK input increments the internal

address counter, if both CE and OE are active.

Pin Name

8-pin

DATA

RESET/OE

CLK

When High, this input holds the address counter reset and

3-states the DATA output. The polarity of this input pin is

programmable as either RESET/OE or OE/RESET. To avoid

confusion, this document describes the pin as RESET/OE,

although the opposite polarity is possible on all devices.

When RESET is active, the address counter is held at zero,

and the DATA output is put in a high-impedance state. The

polarity of this input is programmable. The default is active

High RESET, but the preferred option is active Low RESET,

because it can be driven by the FPGAs INIT pin.

RESET/OE (OE/RESET)

GND

CEO

Capacity

The polarity of this pin is controlled in the programmer inter-

face. This input pin is easily inverted using the Xilinx

HW-130 programmer software. Third-party programmers

have different methods to invert this pin.

Device

Configuration Bits

XC1736D

XC1765D

36,288

65,536

XC17128D

XC17256D

131,072

262,144

When High, this pin disables the internal address counter,

3-states the DATA output, and forces the device into low-I

standby mode.

Number of Configuration Bits, Including

Header for Xilinx FPGAs and Compatible

PROMs

CEO

Chip Enable output, to be connected to the CE input of the

next PROM in the daisy chain. This output is Low when the

CE and OE inputs are both active AND the internal address

counter has been incremented beyond its Terminal Count

(TC) value. In other words: when the PROM has been read,

CEO will follow CE as long as OE is active. When OE goes

inactive, CEO stays High until the PROM is reset. Note that

OE can be programmed to be either active High or active

Low.

Device

Configuration Bits

PROM

XC3000/A series

14,819 to 94,984

XC1765D to

XC17128D

XC4000 series

95,008 to 247,968

XC17128D to

XC17256D

XQ4005E

XQ4010E

XQ4013E

95,008

178,144

247,968

XC17128D

XC17256D

V_PP

Programming voltage. No overshoot above the specified

max voltage is permitted on this pin. For normal read oper-

www.xilinx.com

1-800-255-7778

DS070 (v2.1) June 1, 2000

Product Specification

123 4 5 6 7...10

下载PDF

与X17256256DD8M相关器件

型号	品牌	描述	获取价格	数据表
X1725636DD8M	XILINX	QPRO Family of XC1700D QML Configuration PROMs	获取价格
X1725665DD8B	XILINX	QPRO Family of XC1700D QML Configuration PROMs	获取价格
X1725665DD8M	XILINX	QPRO Family of XC1700D QML Configuration PROMs	获取价格
X-1744036-Y	ETC	Quick Reference Guide Economy Power Connector System	获取价格
X-1744037-Y	ETC	Quick Reference Guide Economy Power Connector System	获取价格
X-1744048-Y	ETC	Quick Reference Guide Economy Power Connector System	获取价格

与X17256256DD8M相关文章

STM32F030C6芯片介绍：主要参数分析、引脚配置说明、功耗及封装
2024-05-11

10
PCF8591数据手册解读：参数、引脚说明
2024-05-11

16
一文带你了解ss8050参数、引脚配置、应用指南
2024-05-11

7
深入解析AD7606高性能多通道模数转换器：资料手册参数分析
2024-05-10

9

产品中心

服务支持

精选活动

关于我们

帮助中心

X17256256DD8M

X17256256DD8M 数据手册

与X17256256DD8M相关器件

与X17256256DD8M相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

X17256256DD8M

X17256256DD8M 数据手册

与X17256256DD8M相关器件

与X17256256DD8M相关文章

您还可以找

您在本页遇到什么问题？