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WS1M8L-25DJIA PDF预览

WS1M8L-25DJIA

更新时间: 2024-01-15 22:43:59
品牌 Logo 应用领域
WEDC 静态存储器
页数 文件大小 规格书
6页 162K
描述
SRAM,

WS1M8L-25DJIA 技术参数

生命周期:Obsolete包装说明:CERAMIC, SOJ-36
Reach Compliance Code:unknown风险等级:5.62
Is Samacsys:N最长访问时间:25 ns
JESD-30 代码:R-CDSO-J36内存密度:8388608 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端子数量:36
字数:1048576 words字数代码:1000000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:1MX8
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
认证状态:Not Qualified最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:J BEND
端子位置:DUALBase Number Matches:1

WS1M8L-25DJIA 数据手册

 浏览型号WS1M8L-25DJIA的Datasheet PDF文件第2页浏览型号WS1M8L-25DJIA的Datasheet PDF文件第3页浏览型号WS1M8L-25DJIA的Datasheet PDF文件第4页浏览型号WS1M8L-25DJIA的Datasheet PDF文件第5页浏览型号WS1M8L-25DJIA的Datasheet PDF文件第6页 
WS1M8-XXX  
HI-RELIABILITY PRODUCT  
2x512Kx8 DUALITHIC™ SRAM  
FEATURES  
Access Times 17, 20, 25, 35, 45, 55ns  
Organized as two banks of 512Kx8  
Revolutionary, Center Power/Ground Pinout  
Commercial, Industrial and Military Temperature Ranges  
5 Volt Power Supply  
Packaging:  
• 32 pin, Hermetic Ceramic DIP (Package 300)  
• 36 lead Ceramic SOJ (Package 100)  
• 36 lead Ceramic Flatpack (Package 226)  
Low Power CMOS  
TTL Compatible Inputs and Outputs  
PIN CONFIGURATION FOR WS1M8-XDJX  
AND WS1M8-XFX  
PIN CONFIGURATION FOR WS1M8-XCX  
32 DIP  
36 CSOJ  
36 FLATPACK  
TOP VIEW  
TOP VIEW  
A18  
A16  
A14  
A12  
A7  
1
32  
VCC  
A0  
A1  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
NC  
2
31 A15  
30 A17  
29 WE  
28 A13  
27 A8  
2
A18  
A17  
A16  
A15  
OE  
3
A2  
3
4
A3  
4
5
A4  
5
A6  
6
CS1  
I/O0  
I/O1  
6
A5  
7
26 A9  
7
I/O7  
I/O6  
GND  
A4  
8
25 A11  
24 CS2  
23 A10  
22 CS1  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
8
A3  
9
VCC  
9
A2  
10  
11  
12  
13  
14  
15  
16  
GND  
I/O2  
I/O3  
WE  
A5  
10  
11  
12  
13  
14  
15  
16  
17  
18  
VCC  
A1  
I/O5  
I/O4  
A14  
A13  
A12  
A11  
A10  
CS2  
A0  
I/O0  
I/O1  
I/O2  
GND  
A6  
A7  
A8  
A9  
PIN DESCRIPTION  
PIN DESCRIPTION  
A0-18  
Address Inputs  
Data Input/Output  
Chip Selects  
Output Enable  
Write Enable  
+5.0V Power  
Ground  
A0-18  
Address Inputs  
Data Input/Output  
Chip Selects  
Write Enable  
+5.0V Power  
Ground  
I/O0-7  
CS1-2  
OE  
WE  
VCC  
I/O0-7  
CS1-2  
WE  
VCC  
GND  
GND  
BLOCK DIAGRAM  
BLOCK DIAGRAM  
I/O0-7  
I/O0-7  
WE  
OE  
0-18  
WE  
0-18  
A
A
512K x 8  
512K x 8  
512K x 8  
512K x 8  
CS1(1)  
CS2(1)  
CS1(1)  
CS2(1)  
NOTE:  
1. CS1 and CS2 are used to select the lower and upper 512Kx8 of the device. CS1 and CS2 must not be enabled at the same time.  
1
October 2000 Rev. 4  
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  

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