Datasheet > WED7G128ATA33ADC25

WED7G128ATA33ADC25

更新时间： 2023-08-15 00:00:00

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WEDC		/
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4页	239K
描述
Flash Memory,

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WED7G128ATA33ADC25 数据手册

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WED7GxxxATA33

White Electronic Designs

PRELIMINARY*

SIGNAL DESCRIPTION

Signal Name

Description

DQ0-DQ7, DQ8-DQ15

Data bus can either be 8-bits or 16-bits wide depending on selection of CE0# and CE1#

CE1# always selects the odd byte of the word. CE0# accesses the even or odd byte depending on A0 and CE1#. For 8-bit

systems, CE0# is used and for 16-bit systems, both CE0# and CE1# are used. Both CE0# and CE1# should be decoded

by the logic to determine the memory window.

CE0#, CE1#

This is an output enable strobe generated by the host interface. It is used to read data from the Flash ChipSet in Memory

Mode and to read the CIS and conﬁguration registers

OE#

The write enable pin is driven by the host and used for strobing data to the registers of the Flash ChipSet when the Flash

ChipSet is conﬁgured in the memory interface mode. It is also used for writing the conﬁguration registers.

WE#

A0-A3 selects the basic registers of the controller to communicate to the module. This requires 16 bytes of host address

space. A0 is optional if CE0# and CE1# are combined to enable 16-bit wide register access.

A0-A10

Busy

The Busy signal is driven low when the product is accessing memory. When Busy is high, register access is allowed. After

a data transfer command is issued, this signal is used to signify that the host can transfer data.

RST

When RST is high, the product is placed in a reset mode. This signal is only valid at power on.

This signal is driven high since a battery is not used with this product

This output line is always driven to a high state in Memory Mode since a batery is not required for this product

This signal is not used in the memory mode.

BVD1

BVD2

IOWR

IORD

This signal is not used in the memory mode.

This signal is used during Memory Cycles to distinguish between common memory and register memory accesses. High

for common memory, low for attribute memory.

REG

INPACK

IO16

This signal is not used in the memory mode.

Optional test signals not used in the Memory Mapped Mode.

Pins are reserved for future expansion and must be left ﬂoating.

Power pins. All V_CCpins must be connected.

Reserved

V_CC

V_SS

Ground pins. All V_SSpins must be connected.

No connect. Pin internally not connected.

BLOCK DIAGRAM

A0 - A10

CE0

D0 - D7

Data

SanDisk

Controller

Control

NAND

Flash

D8 - D15

CE1

Control signals used

in other modes (see

pin list)

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

July, 2002

Rev. 0

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 234

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