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VSC7959W

更新时间: 2024-01-06 21:27:03
品牌 Logo 应用领域
VITESSE 放大器瞄准线
页数 文件大小 规格书
10页 99K
描述
3.125Gb/s CML Limiting Amplifier with LOS Detect

VSC7959W 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:TSSOP, TSSOP16,.25Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.43
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:3.3/5 V
认证状态:Not Qualified子类别:ATM/SONET/SDH ICs
表面贴装:YES技术:GAAS
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
Base Number Matches:1

VSC7959W 数据手册

 浏览型号VSC7959W的Datasheet PDF文件第4页浏览型号VSC7959W的Datasheet PDF文件第5页浏览型号VSC7959W的Datasheet PDF文件第6页浏览型号VSC7959W的Datasheet PDF文件第8页浏览型号VSC7959W的Datasheet PDF文件第9页浏览型号VSC7959W的Datasheet PDF文件第10页 
VITESSE  
SEMICONDUCTOR CORPORATION  
Advance Product Information  
3.125Gb/s CML Limiting Amplifier with LOS Detect  
VSC7959  
Detailed Description  
The VSC7959 is a high speed limiting amplifier with Loss-of-Signal (LOS) detect. The device is designed  
to operate with a 3.3V or 5V supply in SDH/SONET and Fibre Channel applications up to 3.125Gb/s. The  
VSC7959 has current-mode logic (CML) outputs. The VSC7961 provides the same functionality as the  
VSC7959 with positive emitter-coupled logic (PECL) outputs. The key features of the VSC7959 are Loss-of-  
Signal (LOS) detect, output offset correction, output squelch, adjustable output levels, low power supply cur-  
rent, and fast rise and fall times.  
The inputs of the device provide 100input impedance between IN+ and IN- and are intended to be DC-  
coupled. The CML output circuits are designed to tolerate output impedance mismatches and may be AC- or  
DC-coupled.  
Loss of Signal (LOS) Detect  
This features utilizes an RMS power detector with programmable LOS indicator to provide two outputs,  
LOS and LOS. The input TH is used to set the threshold at which the loss of signal detector outputs, LOS and  
LOS, change state. See the Loss of Signal Specifications (Table 3) for setting the resistor value between TH and  
ground. The Loss of Signal Truth Table (Table 4) clarifies how LOS and SQUELCH interact.  
Optional Squelch  
Squelch is disabled when SQUELCH is not connected or is set to TTL low level. When SQUELCH is set to  
TTL high level and LOS is asserted, the data outputs, OUT+ and OUT- are forced to static levels. If LOS is not  
asserted, the outputs will not be squelched.  
Offset Correction  
This feature is provided to ensure that the offsets in the limiting amplifier coupled with its gain do not cause  
the output buffer to give a false output. Because of the high gain of the amplifier, offset correction using a low-  
frequency feedback loop reduces input offset. If no component is placed between pins CZ1 and CZ2, the low  
frequency cut-off is 2MHz. If a 0.1µF capacitor is placed between CZ1 and CZ2, the low frequency cut-off is  
lowered to about 2kHz. For Fibre Channel and Gigabit Ethernet applications, leave pins CZ1 and CZ2 open. For  
ATM/SONET and other scrambled non-return-to-zero (NRZ) applications, place a 0.1µF capacitor between  
CZ1 and CZ2. This maintains a one-decade separation between the lowest input frequency and the low fre-  
quency cut-off. The low frequency cut-off of the offset correction loop is given by the following equation:  
f
= 43 / [2π * 35k (C + 100pF)]  
OC  
Z
-6  
= 196 10 / (C + 100pF)  
Z
-6  
= 196 10 / (0.1µF + 100pF)  
= 1.96kHz  
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012  
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com  
Internet: www.vitesse.com  
G52358-0, Rev 2.0  
02/09/01  
Page 7  

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