Datasheet > VSC6424QW

VSC6424QW

更新时间： 2024-02-26 21:31:09

品牌	Logo	应用领域
VITESSE		外围集成电路
页数	文件大小	规格书
18页	364K
描述
Video Shift Register, 10-Bit, CMOS, PQFP128, 14 X 20 MM, PLASTIC, QFP-128

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VSC6424QW 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	FQFP,	针数：	128
Reach Compliance Code：	compliant	风险等级：	5.73
边界扫描：	NO	外部数据总线宽度：	10
JESD-30 代码：	R-PQFP-G128	长度：	20 mm
低功率模式：	NO	端子数量：	128
最高工作温度：	70 °C	最低工作温度：
输出数据总线宽度：	8	封装主体材料：	PLASTIC/EPOXY
封装代码：	FQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	3.4 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	14 mm	uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, VIDEO SHIFT REGISTER
Base Number Matches：	1

VSC6424QW 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

500 Mb/s Video

Shift Register IC

VSC6424

Functional Description

The VSC6424 is a 40-bit user configurable shift register designed to provide general purpose serialization

or de-serialization for high speed designs. The VSC6424 provides both multiplexer (MUX) and demultiplexer

(DEMUX) operations in a single package. With the ability to generate timing signals internally or have them

provided externally the VSC6424 maintains the highest design flexibility.

The low speed signals (parallel data, configuration, external timing) use a TTL interface and the high-speed

signals (serial data, high-speed clock) use an ECL interface. Two power supplies are utilized, +3.3 Volts and -2

Volts, dissipating a maximum of 2.7 Watts. A -1.32V external reference voltage is necessary for the ECL inter-

face. The part is packaged in a 14mm x 20mm 128-pin plastic quad flat pack with an exposed heat spreader.

Shift Register Mode/Modulus Selection

The shift register can be setup to work as multiplexer or as a demultiplexer. The MODE pin controls the

direction of operation (MUX or DEMUX). The select pins S<0:2> put the shift register in one of 8 configura-

tions shown in Table 1

Table 1: Modulus of Operation

Multiplexer

MODE = 0

Demultiplexer

MODE = 1

8 4:1

8 5:1

10 1:4

8 1:5

5 8:1

5 1:8

4 10:1

2 16:1

2 20:1

1 32:1

1 40:1

4 1:10

2 1:16

2 1:20

1 1:32

1 1:40

Internal Timing

The VSC6424 can be set up to use either internal or external timing sources. The VSC6424 contains an

internal timing generator that provides load and output rates depending on the modulus selected for the shift

be used for designs above 250MHz.

The internal timing generator also provides two low-speed clock outputs, CLKT(TTL) and CLKE(ECL).

The low speed clock is brought out so that other ICs can use this to latch the low speed data while in DMUX

mode. The slow speed clock output can be the same as the internal clock, or 1/2 the internal frequency by set-

ting DIVC high. These outputs can also be shifted in 45 degree increments, using the phase select pins

SP<0:2>, to allow compensation for trace delays on the board. Phase rotation is not available in divide by 5 or

divide by 10 modes.

The internal high speed clock is also brought out to a differential ECL output (CLKOUT). This output is

provided for clocking of the high speed data into the next IC.

Page 2

VITESSE SEMICONDUCTOR CORPORATION

G52236-0, Rev 3.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

7/13/99

123 4 5 6 7...18

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与VSC6424QW相关器件

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VSC7101FC-1	ETC	获取价格	Fiber-Optic Transmitter
VSC7101FC-1.2	ETC	获取价格	Fiber-Optic Transmitter
VSC7102FC-1	VITESSE	获取价格	Telecom IC, GAAS, CQFP28,
VSC7102FC-1.2	VITESSE	获取价格	Telecom IC, GAAS, CQFP28,
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VSC7104	VITESSE	获取价格	Quad Signal Conditioner, Octal Signal Conditioner

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