V55C2256164VB
256Mbit MOBILE SDRAM
2.5 VOLT FBGA PACKAGE 16M X 16
7
8PC
10
100MHz
10 ns
7 ns
System Frequency (fCK
Clock Cycle Time (tCK3
)
143 MHz
7 ns
125 MHz
8 ns
)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
Clock Access Time (tAC1) CAS Latency = 1
5.4 ns
6 ns
6 ns
6 ns
8 ns
19 ns
19 ns
22 ns
■ Programmable Power Reduction Feature by par-
tial array activation during Self-Refresh
■ Operating Temperature Range
Commercial (0°C to 70°C)
Features
■ 4 banks x 4Mbit x 16 organization
■ High speed data transfer rates up to 143 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Industrial (-40°C to +85°C)
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency:1, 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Power Down Mode and Clock Suspend Mode
■ Deep Power Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 8192 cycles/64 ms
■ Available in 54-ball FBGA, with 9x6 ball array
with 3 depupulated rows, 13x8 mm and 54 pin
TSOP II
■ VDD=2.5V, VDDQ=1.8V
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Temperature
C/T
7
•
8PC
10
Mark
0°C to 70°C
•
•
•
•
•
•
Commercial
Extended
-40°C to 85°C
•
V55C2256164VB Rev. 1.0 April 2005
1