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UPD780111GB(A)-XXX-8ES-A PDF预览

UPD780111GB(A)-XXX-8ES-A

更新时间: 2023-02-26 14:46:11
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟ISM频段外围集成电路
页数 文件大小 规格书
536页 3127K
描述
8-BIT, MROM, 10MHz, MICROCONTROLLER, PQFP44, 10 X 10 MM, PLASTIC, LQFP-44

UPD780111GB(A)-XXX-8ES-A 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:44
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.64具有ADC:YES
其他特性:ALSO OPERATES AT 2.7V MINIMUM SUPPLY地址总线宽度:
位大小:8最大时钟频率:10 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:S-PQFP-G44
长度:10 mmI/O 线路数量:32
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
认证状态:Not QualifiedROM可编程性:MROM
座面最大高度:1.6 mm速度:10 MHz
最大供电电压:5.5 V最小供电电压:4 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD宽度:10 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER

UPD780111GB(A)-XXX-8ES-A 数据手册

 浏览型号UPD780111GB(A)-XXX-8ES-A的Datasheet PDF文件第2页浏览型号UPD780111GB(A)-XXX-8ES-A的Datasheet PDF文件第3页浏览型号UPD780111GB(A)-XXX-8ES-A的Datasheet PDF文件第4页浏览型号UPD780111GB(A)-XXX-8ES-A的Datasheet PDF文件第6页浏览型号UPD780111GB(A)-XXX-8ES-A的Datasheet PDF文件第7页浏览型号UPD780111GB(A)-XXX-8ES-A的Datasheet PDF文件第8页 
NOTES FOR CMOS DEVICES  
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN  
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the  
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may  
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,  
and also in the transition period when the input level passes through the area between VIL (MAX) and  
VIH (MIN).  
HANDLING OF UNUSED INPUT PINS  
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is  
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS  
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed  
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND  
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must  
be judged separately for each device and according to related specifications governing the device.  
3
PRECAUTION AGAINST ESD  
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and  
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as  
much as possible, and quickly dissipate it when it has occurred. Environmental control must be  
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that  
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static  
container, static shielding bag or conductive material. All test and measurement tools including work  
benches and floors should be grounded. The operator should be grounded using a wrist strap.  
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for  
PW boards with mounted semiconductor devices.  
4
STATUS BEFORE INITIALIZATION  
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power  
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does  
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the  
reset signal is received. A reset operation must be executed immediately after power-on for devices  
with reset functions.  
5
POWER ON/OFF SEQUENCE  
In the case of a device that uses different power supplies for the internal operation and external  
interface, as a rule, switch on the external power supply after switching on the internal power supply.  
When switching the power supply off, as a rule, switch off the external power supply and then the  
internal power supply. Use of the reverse power on/off sequences may result in the application of an  
overvoltage to the internal elements of the device, causing malfunction and degradation of internal  
elements due to the passage of an abnormal current.  
The correct power on/off sequence must be judged separately for each device and according to related  
specifications governing the device.  
6
INPUT OF SIGNAL DURING POWER OFF STATE  
Do not input signals or an I/O pull-up power supply while the device is not powered. The current  
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and  
the abnormal current that passes in the device at this time may cause degradation of internal elements.  
Input of signals during the power off state must be judged separately for each device and according to  
related specifications governing the device.  
3
User’s Manual U16227EJ3V0UD  

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