Page 6
3.2 UM245R Signal Descriptions
Table 1 - Module Pin Out Description
Pin No. Name
Type Description
1
2
3
4
DB0
DB4
DB2
VIO
I/O
FIFO Data Bus Bit 0*
I/O
FIFO Data Bus Bit 4*
I/O
FIFO Data Bus Bit 2*
PWR
+1.8V to +5.25V supply to the FIFO Interface and Control group pins (1...3, 5, 6, 9...14, 22, 23).
In USB bus powered designs connect to 3V3OUT to drive out at 3.3V levels (connect jumper J1 pins 1 and 2
together), or connect to VCC to drive out at 5V CMOS level (connect jumper J1 pins 2 and 3 together). This
pin can also be supplied with an external 1.8V - 2.8V supply in order to drive out at lower levels. It should be
noted that in this case this supply should originate from the same source as the supply to Vcc. This means
that in bus powered designs a regulator which is supplied by the 5V on the USB bus should be used.
5
DB5
DB7
GND
DB5
DB6
DB3
PWE#
I/O
FIFO Data Bus Bit 1*
FIFO Data Bus Bit 7*
Module ground supply pins
FIFO Data Bus Bit 5*
FIFO Data Bus Bit 6*
FIFO Data Bus Bit 3*
6
I/O
7, 24
8
PWR
I/O
9
I/O
10
11
I/O
I/O
Goes low after the device is configured by USB, then high during USB suspend. Can be used to control power
to external logic P-Channel logic level MOSFET switch. Enable the interface pull-down option when using the
PWREN# pin in this way.
12
RD#
I/O
Enables the current FIFO data byte on D0...D7 when low. Fetched the next FIFO data byte (if available) from
the receive FIFO buffer when RD# goes from high to low. See Section 3.4 for timing diagram.*
13
14
SLD
USB
GND
USB Cable shield.
Output 5V Power output USB port. For a low power USB bus powered design, up to 100mA can be sourced from the
5V supply on the USB bus. A maximum of 500mA can be sourced from the USB bus in a high power USB bus
powered design.
15, 21
VCC
PWR
or
These two pins are internally connected on the module pcb. To power the module from the 5V supply on USB
bus connect jumper J2 pins 1 and 2 together (this is the module default configuration). In this case these pins
Output would have the same description as pin 14.
To use the UM245R module in a self powered configuration ensure that jumper J2 pins 1 and 2 are not con-
nected together, and apply an external 3.3V to 5.25V supply to one or both of these pins.
16
17
19
PU2
PU1
3V3
Control Pull up resistor pin connection 2. Conect to pin 17 (RST#) in a self powered configuration.
Control Pull up resistor pin connection 1. Connect to pin 14 (USB) in a self powered configuration.
Output 3.3V output from integrated L.D.O. regulator. This pin is decoupled to ground on the module pcb with a 10nF
capacitor. The prime purpose of this pin is to provide the internal 3.3V supply to the USB transceiver cell and
the internal 1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if
required. This pin can also be used to supply the FT245RL’s VCCIO pin by connecting this pin to pin 4 (VIO),
or by connecting together pins 1 and 2 on jumper J1.
20
18
22
RST#
WR
Input
Can be used by an external device to reset the FT245R. If not required can be left unconnected, or pulled up
to VCCIO.
I/O
Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR goes from high to low. See
Section 3.4 for timing diagram.*
TXE#
I/O
When high, do not write data into the FIFO. When low, data can be written into the FIFO by strobing WR high,
then low. During reset this signal pin is tri-state, but pulled up to VCCIO via an internal 200kΩ resistor. See
Section 3.4 for timing diagram.
23
RXF#
I/O
When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read
by strobing RD# low, then high again. During reset this signal pin is tri-state, but pulled up to VCCIO via an
internal 200kΩ resistor. See Section 3.4 for timing diagram.
If the Remote Wakeup option is enabled in the internal EEPROM, during USB suspend mode (PWREN# = 1)
RXF# becomes an input which can be used to wake up the USB host from suspend mode. Strobing the pin
low will cause the device to request a resume on the USB bus.
* When used in Input Mode, these pins are pulled to VCCIO via internal 200kΩ resistors. These can be programmed
to gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the internal EEPROM.
UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02
© Future Technology Devices International Ltd. 2005
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