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TOP225

更新时间: 2024-01-27 06:36:54
品牌 Logo 应用领域
帕沃英蒂格盛 - POWERINT /
页数 文件大小 规格书
20页 1537K
描述
Three-Terminal Off-Line PWM Switch

TOP225 技术参数

是否Rohs认证: 符合生命周期:Not Recommended
零件包装代码:SFM包装说明:TO-220, 3 PIN
针数:3Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:14 weeks风险等级:8.45
模拟集成电路 - 其他类型:SWITCHING REGULATOR控制模式:VOLTAGE-MODE
控制技术:PULSE WIDTH MODULATIONJESD-30 代码:R-PSFM-T3
功能数量:1端子数量:3
最高工作温度:125 °C最低工作温度:-40 °C
最大输出电流:2.2 A封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:FLANGE MOUNT
认证状态:Not Qualified表面贴装:NO
切换器配置:BOOST最大切换频率:110 kHz
技术:CMOS温度等级:AUTOMOTIVE
端子形式:THROUGH-HOLE端子位置:SINGLE

TOP225 数据手册

 浏览型号TOP225的Datasheet PDF文件第4页浏览型号TOP225的Datasheet PDF文件第5页浏览型号TOP225的Datasheet PDF文件第6页浏览型号TOP225的Datasheet PDF文件第8页浏览型号TOP225的Datasheet PDF文件第9页浏览型号TOP225的Datasheet PDF文件第10页 
TOP221-227  
ꢗ1  
ꢅ.ꢅ µꢙ  
ꢇꢃ  
ꢈꢉRꢊꢃ0  
ꢌ12 ꢍ  
ꢅTꢁ  
ꢌꢃ  
ꢅꢅ0 µꢍ  
ꢅꢎ ꢏ  
ꢌꢅ  
ꢃꢃ0 µꢍ  
ꢅꢎ ꢏ  
ꢏR1  
ꢀ6ꢓꢔꢃ00  
ꢇ1  
ꢑꢒꢏꢃ6ꢌ  
ꢑR1  
ꢊ00 ꢏ  
ꢗꢃ  
ꢃꢃ ꢘꢙ  
ꢇꢅ  
1ꢋꢊ1ꢊ8  
R1  
ꢌ1  
100 Ω  
ꢊꢆ µꢍ  
ꢌꢊ  
0.1 µꢍ  
ꢊ00 ꢏ  
TOPꢃꢆꢇꢈꢉꢊ-ꢋꢋ  
ꢌ6  
Rꢃ  
ꢉ1  
0.1 µꢍ  
ꢐ1  
ꢃꢃ0 Ω  
ꢐꢚꢀꢃꢃꢊꢀ  
ꢄOꢁTꢅOꢀ  
ꢃꢎ0 ꢏꢕꢌ  
ꢉꢃ  
ꢀꢌ81ꢆꢕ  
Rꢅ  
6.8 Ω  
ꢍ1  
ꢅ.1ꢎ ꢕ  
ꢏRꢃ  
1ꢋꢎꢃꢊ1ꢑ  
11 ꢏ  
ꢌꢆ  
1 ꢛꢍ  
ꢃꢎ0 ꢏꢕꢌ  
ꢒ1  
ꢖ1  
ꢌꢎ  
ꢊꢆ µꢍ  
ꢀꢁꢂꢃ01ꢄꢂ0ꢅꢅ1ꢄꢆ  
Figure 8. Schematic Diagram of a 20 W Universal Input TOPSwitch-II Power Supply using an 8 lead PDIP.  
20 W Universal Supply using 8 Lead PDIP  
VR1 clamp leading-edge voltage spikes caused by trans-  
former leakage inductance. The power secondary winding  
is rectified and filtered by D2, C2, L1, and C3 to create the  
12 V output voltage. R2 and VR2 provide a slight pre-load  
on the 12 V output to improve load regulation at light loads.  
The bias winding is rectified and filtered by D3 and C4 to  
create a TOPSwitch bias voltage. L2 and Y1-safety capaci-  
tor C7 attenuate common mode emission currents caused  
by high-voltage switching waveforms on the DRAIN side of  
the primary winding and the primary to secondary capaci-  
tance. Leakage inductance of L2 with C1 and C6 attenu-  
ates differential-mode emission currents caused by the  
fundamental and harmonics of the trapezoidal or triangular  
primary current waveform. C5 filters internal MOSFET gate  
drive charge current spikes on the CONTROL pin, deter-  
mines the auto-restart frequency, and together with R1 and  
R3, compensates the control loop.  
Figure 8 shows a 12 V, 20 W secondary regulated flyback  
power supply using the TOP224P in an eight lead PDIP  
package and operating from universal 85 to 265 VAC input  
voltage. This example demonstrates the advantage of the  
higher power 8 pin leadframe used with the TOPSwitch-II  
family. This low cost package transfers heat directly to the  
board through six source pins, eliminating the heatsink and  
the associated cost. Efficiency is typically 80% at low line  
input. Output voltage is directly sensed by optocoupler U2  
and Zener diode VR2. The output voltage is determined by  
the Zener diode (VR2) voltage and the voltage drops across  
the optocoupler (U2) LED and resistor R1. Other output  
voltages are possible by adjusting the transformer turns ratio  
and value of Zener diode VR2.  
AC power is rectified and filtered by BR1 and C1 to create  
the high voltage DC bus applied to the primary winding of  
T1. The other side of the transformer primary is driven by  
the integrated TOPSwitch-II high-voltage MOSFET. D1 and  
7
Rev. G 08/16  
www.power.com  

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