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TLV5535IPWG4 PDF预览

TLV5535IPWG4

更新时间: 2024-01-27 06:56:25
品牌 Logo 应用领域
德州仪器 - TI 光电二极管转换器
页数 文件大小 规格书
35页 723K
描述
8-Bit, 35-MSPS Analog-to-Digital Converter (ADC) 28-TSSOP -40 to 85

TLV5535IPWG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:TSSOP, TSSOP28,.25针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.44
最大模拟输入电压:3.5 V最小模拟输入电压:0.8 V
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:R-PDSO-G28
JESD-609代码:e4长度:9.7 mm
最大线性误差 (EL):0.9375%湿度敏感等级:1
模拟输入通道数量:1位数:8
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:BINARY输出格式:PARALLEL, 8 BITS
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
采样速率:35 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.2 mm子类别:Analog to Digital Converters
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

TLV5535IPWG4 数据手册

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TLV5535  
8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER  
SLAS221 – JUNE 1999  
electrical characteristics over recommended operating conditions, f  
voltage references (unless otherwise noted) (continued)  
= 35 MSPS, external  
CLK  
timing requirements  
PARAMETER  
Maximum conversion rate  
Minimum conversion rate  
Output delay time (see Figure 1)  
Output hold time  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
MHz  
kHz  
ns  
35  
f
CLK  
10  
9
t
t
C
C
= 10 pF,  
= 2 pF,  
See Notes 5 and 6  
See Note 5  
d(o)  
L
L
2
ns  
h(o)  
CLK  
cycles  
t
Pipeline delay time (latency)  
See Note 6  
4.5  
4.5  
4.5  
d(pipe)  
t
t
t
t
Aperture delay time  
3
1.5  
5
ns  
ps, rms  
ns  
d(a)  
j(a)  
dis  
en  
Aperture jitter  
See Note 5  
Disable time, OE rising to Hi-Z  
Enable time, OE falling to valid data  
8
8
5
ns  
NOTES: 5. Outputtiming t  
d(o)  
is measured from the 1.5 V level oftheCLKinputfallingedgetothe10%/90%levelofthedigitaloutput. Thedigital  
output load is not higher than 10 pF.  
Output hold time t is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The  
h(o)  
digital output is load is not less than 2 pF.  
Aperture delay t is measured from the 1.5 V level of the CLK input to the actual sampling instant.  
d(A)  
The OE signal is asynchronous.  
OE timing t is measured from the V  
level of OE to the high-impedance state of the output data. The digital output load is  
dis IH(MIN)  
not higher than 10 pF.  
OE timing t is measured from the V  
levels. The digital output load is not higher than 10 pF.  
level of OE to the instant when the output data reaches V  
OH(min)  
or V  
output  
OL(max)  
en IL(MAX)  
6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made  
available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to  
know when data is stable on the output pins, the output delay time t  
(i.e., the delay time through the digital output buffers) needs  
is more than 1/2 clock period at 35 MHz, data cannot be reliably  
d(o)  
to be added to the pipeline latency. Note that since the max t  
d(o)  
clocked in on a rising edge of CLK at this speed. The falling edge should be used.  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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