Datasheet > 逻辑 > 触发器/锁存器> 5962-8515301CA

5962-8515301CA

更新时间： 2024-02-15 11:21:19

品牌	Logo	应用领域
德州仪器 - TI		触发器锁存器逻辑集成电路
页数	文件大小	规格书
13页	278K
描述
Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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5962-8515301CA 技术参数

生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	14
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.72	Is Samacsys：	N
其他特性：	MASTER SLAVE OPERATION	系列：	HC/UH
JESD-30 代码：	R-GDIP-T14	逻辑集成电路类型：	J-K FLIP-FLOP
位数：	2	功能数量：	2
端子数量：	14	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出极性：	COMPLEMENTARY
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
传播延迟（tpd）：	255 ns	认证状态：	Qualified
筛选级别：	MIL-STD-883	座面最大高度：	5.08 mm
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	4.5 V	表面贴装：	NO
技术：	CMOS	温度等级：	MILITARY
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	触发器类型：	NEGATIVE EDGE
宽度：	7.62 mm	最小 fmax：	32 MHz
Base Number Matches：	1

5962-8515301CA 数据手册

CD54HC73, CD74HC73,

CD74HCT73

Data sheet acquired from Harris Semiconductor

SCHS134E

Dual J-K Flip-Flop with Reset

Negative-Edge Trigger

February 1998 - Revised September 2003

Features

Description

• Hysteresis on Clock Inputs for Improved Noise

Immunity and Increased Input Rise and Fall Times

The ’HC73 and CD74HCT73 utilize silicon gate CMOS

technology to achieve operating speeds equivalent to LSTTL

parts. They exhibit the low power consumption of standard

CMOS integrated circuits, together with the ability to drive 10

LSTTL loads.

[ /Title

(CD74

HC73,

CD74

HCT73

)

• Asynchronous Reset

• Complementary Outputs

• Buffered Inputs

These ﬂip-ﬂops have independent J, K, Reset and Clock

inputs and Q and Q outputs. They change state on the

negative-going transition of the clock pulse. Reset is

accomplished asynchronously by a low level input. This

device is functionally identical to the HC/HCT107 but differs

in terminal assignment and in some parametric limits.

• Typical f

MAX

= 60MHz at V = 5V, C = 15pF,

CC L

T = 25 C

/Sub-

ject

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

(Dual

J-K

Flip-

Flop

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible

with the standard LS logic family.

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

Ordering Information

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

TEMP. RANGE

PART NUMBER

CD54HC73F3A

CD74HC73E

( C)

PACKAGE

14 Ld CERDIP

14 Ld PDIP

14 Ld SOIC

14 Ld PDIP

14 Ld SOIC

-55 to 125

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74HC73M

at V

= 5V

CD74HC73MT

CD74HC73M96

CD74HCT73E

CD74HCT73M

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

Pinout

CD54HC73 (CERDIP)

CD74HC73, CD74HCT73 (PDIP, SOIC)

TOP VIEW

1CP

14 1J

13 1Q

12 1Q

11 GND

10 2K

2CP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...13

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5962-8515401CA	TI	Dual J-K Flip-Flop with Reset Negative-Edge Trigger	获取价格
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