TDA3MV, TDA3MA, TDA3MD
TDA3LX, TDA3LA
ZHCSH24G –JUNE 2016–REVISED MARCH 2019
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 .................................................. 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能框图 ............................................. 3
修订历史记录............................................... 5
Device Comparison ..................................... 6
3.1 Related Products ..................................... 8
Terminal Configuration and Functions.............. 9
4.1 Terminal Assignment ................................. 9
4.2 Ball Characteristics.................................. 10
4.3 Multiplexing Characteristics ......................... 40
4.4 Signal Descriptions.................................. 51
Specifications .......................................... 75
5.1 Absolute Maximum Ratings......................... 76
5.2 ESD Ratings ........................................ 76
5.3 Power On Hour (POH) Limits ....................... 77
5.4 Power on Hour (POH) Limits........................ 77
5.5 Recommended Operating Conditions............... 78
5.6 Operating Performance Points ...................... 80
5.7 Power Consumption Summary...................... 90
5.8 Electrical Characteristics ............................ 91
7.8 External Memory Interface (EMIF)................. 127
7.9
General-Purpose Memory Controller (GPMC)..... 127
7.10 General-Purpose Timers........................... 148
7.11 Inter-Integrated Circuit Interface (I2C)............. 148
7.12 Universal Asynchronous Receiver Transmitter
(UART) ............................................. 151
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7.13 Multichannel Serial Peripheral Interface (McSPI) . 153
7.14 Quad Serial Peripheral Interface (QSPI) .......... 159
7.15 Multichannel Audio Serial Port (McASP) .......... 163
7.16 Controller Area Network Interface (DCAN and
MCAN) ............................................. 171
7.17 Ethernet Interface (GMAC_SW) ................... 172
7.18 SDIO Controller .................................... 176
7.19 General-Purpose Interface (GPIO) ................ 181
7.20 Test Interfaces ..................................... 182
Applications, Implementation, and Layout ...... 185
8.1 Introduction ........................................ 185
8.2 Power Optimizations ............................... 186
8.3 Core Power Domains .............................. 197
8.4 Single-Ended Interfaces ........................... 206
8.5 Differential Interfaces .............................. 209
8.6 Clock Routing Guidelines .......................... 211
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8
8.7
8.8
8.9
LPDDR2 Board Design and Layout Guidelines.... 212
DDR2 Board Design and Layout Guidelines....... 220
DDR3 Board Design and Layout Guidelines....... 232
5.9 Thermal Characteristics ............................. 97
5.10 Analog-to-Digital ADC Subsystem Electrical
Specifications........................................ 98
8.10 CVIDEO/SD-DAC Guidelines and Electrical
5.11 Power Supply Sequences ......................... 100
Clock Specifications ................................. 106
6.1 Input Clock Specifications ......................... 107
6.2 DPLLs, DLLs Specifications ....................... 112
Data/Timing ........................................ 255
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Device and Documentation Support.............. 257
9.1 Device Nomenclature .............................. 257
9.2 Tools and Software ................................ 259
9.3 Documentation Support............................ 261
9.4 Related Links ...................................... 261
9.5 Community Resources............................. 261
9.6 商标 ................................................ 261
9.7 静电放电警告....................................... 261
9.8 Export Control Notice .............................. 262
9.9 Glossary............................................ 262
Timing Requirements and Switching
Characteristics ........................................ 116
7.1 Timing Test Conditions ............................ 116
7.2 Interface Clock Specifications ..................... 116
7.3 Timing Parameters and Information ............... 116
7.4
Recommended Clock and Control Signal Transition
Behavior............................................ 118
7.5 Video Input Ports (VIP) ............................ 119
10 Mechanical, Packaging, and Orderable
7.6
Display Subsystem – Video Output Ports ......... 124
Information............................................. 263
10.1 Packaging Information ............................. 263
7.7 Imaging Subsystem (ISS).......................... 126
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