Datasheet > TC74AC139F_12

TC74AC139F_12

更新时间： 2022-04-06 02:39:30

品牌	Logo	应用领域
东芝 - TOSHIBA		解码器
页数	文件大小	规格书
8页	233K
描述
Dual 2-to-4 Line Decoder

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数据手册

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TC74AC139F_12 数据手册

TC74AC139P/F/FT

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74AC139P,TC74AC139F,TC74AC139FT

Dual 2-to-4 Line Decoder

The TC74AC139 is an advanced high speed CMOS 2-to-4 LINE

DECODER fabricated with silicon gate and double-layer metal

wiring C²MOS technology.

It achieves the high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low power

dissipation.

The active low enable input can be used for gating or it can be

used as a data input for demultiplexing applications.

When the enable input is held “H”, all four outputs are fixed at

a high logic level independent of the other inputs.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

TC74AC139P

TC74AC139F

TC74AC139FT

Features

•

High speed: t = 5.9 ns (typ.) at V

= 5 V

Low power dissipation: I

= 8 μA (max) at Ta = 25°C

High noise immunity: V

= V

= 28% V

(min)

NIH

NIL

Symmetrical output impedance:

|I | = I = 24 mA (min) Capability of driving 50 Ω

transmission lines.

∼

−

pHL

(opr) = 2 V to 5.5 V

•

Balanced propagation delays: t

pLH

Wide operating voltage range: V

Pin and function compatible with 74F139

Pin Assignment

Weight

15 2G

14 2A

DIP16-P-300-2.54A

SOP16-P-300-1.27A

TSSOP16-P-0044-0.65A

: 1.00 g (typ.)

: 0.18 g (typ.)

: 0.06 g (typ.)

1Y0

13 2B

1Y1

1Y2

12 2Y0

11 2Y1

10 2Y2

1Y3

GND

2Y3

(top view)

2012-02-29

12 3 4 5 6 7 8

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