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TC4222CG#PBF PDF预览

TC4222CG#PBF

更新时间: 2024-02-04 03:52:53
品牌 Logo 应用领域
凌特 - Linear 光电二极管
页数 文件大小 规格书
32页 277K
描述
IC 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO36, 5.30 MM, LEAD FREE, PLASTIC, SSOP-36, Power Management Circuit

TC4222CG#PBF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:5.30 MM, LEAD FREE, PLASTIC, SSOP-36针数:36
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
可调阈值:NO模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码:R-PDSO-G36长度:12.8 mm
湿度敏感等级:1信道数量:2
功能数量:1端子数量:36
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP36,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:12 V认证状态:Not Qualified
座面最大高度:2 mm子类别:Power Management Circuits
最大供电电流 (Isup):4 mA最大供电电压 (Vsup):29 V
最小供电电压 (Vsup):2.9 V标称供电电压 (Vsup):12 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

TC4222CG#PBF 数据手册

 浏览型号TC4222CG#PBF的Datasheet PDF文件第2页浏览型号TC4222CG#PBF的Datasheet PDF文件第3页浏览型号TC4222CG#PBF的Datasheet PDF文件第4页浏览型号TC4222CG#PBF的Datasheet PDF文件第6页浏览型号TC4222CG#PBF的Datasheet PDF文件第7页浏览型号TC4222CG#PBF的Datasheet PDF文件第8页 
LTC4222  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
2
I C Interface  
l
l
V
ADR0, ADR1, ADR2 Input High Voltage  
ADR0, ADR1, ADR2 Hi-Z Input Current  
INTV  
INTV  
INTV  
CC  
V
ADR(H)  
CC  
CC  
– 0.8  
– 0.4  
– 0.2  
I
ADR0, ADR1, ADR2 = 0.8V,  
5
0
–5  
μA  
ADR(IN,Z)  
INTV – 0.8V  
CC  
l
l
l
l
l
l
l
V
ADR0, ADR1, ADR2 Input Low Voltage  
ADR0, ADR1, ADR2 Input Current  
ALERT Output Low Voltage  
ALERT Input Current  
0.2  
0.4  
0.2  
1.7  
0.2  
0.8  
80  
0.4  
1
V
μA  
V
ADR(L)  
I
ADR0, ADR1, ADR2 = 0V, INTV  
–80  
ADR(IN)  
CC  
V
I
= 3mA  
ALERT  
ALERT(OL)  
ALERT(OH)  
I
ALERT = INTV  
μA  
V
CC  
V
SDA, SCL Input Threshold  
SDA, SCL Input Current  
1.5  
1.9  
1
SDA,SCL(TH)  
I
SCL, SDA = INTV  
μA  
V
SDA,SCL(OH)  
CC  
V
SDA Output Low Voltage  
I
= 3mA  
SDA  
0.4  
SDA(OL)  
2
I C Interface Timing  
f
t
t
t
t
t
t
t
t
t
SCL Clock Frequency  
Operates with f  
≤ f  
SCL(MAX)  
400  
1000  
0.12  
100  
30  
kHz  
μs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
pF  
SCL(MAX)  
BUF(MIN)  
HD,STA(MIN)  
SU,STA(MIN)  
SU,STO(MIN)  
HD,DAT(MIN)  
HD,DATO  
SCL  
Bus Free Time Between Stop/Start Condition  
Hold Time After (Repeated) Start Condition  
Repeated Start Condition Set-Up Time  
Stop Condition Set-Up Time  
Data Hold Time (Input)  
1.3  
600  
600  
600  
100  
900  
600  
250  
40  
140  
30  
Data Hold Time (Output)  
300  
600  
30  
Data Set-Up Time  
SU,DAT(MIN)  
SP  
Suppressed Spike Pulse Width  
Stuck-Bus Reset Time  
50  
25  
110  
32  
SCL or SDA Held Low  
SDAI Tied to SDAO (Note 5)  
RST  
C
SCL, SDA Input Capacitance  
10  
X
Note 1: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
Note 2: All currents into pins are positive, all voltages are referenced to  
GND unless otherwise specified.  
Note 3: An internal clamp limits the GATE pin to a minimum of 5V above  
SOURCE. Driving this pin to voltages beyond the clamp may damage the  
device.  
Note 4: Integral Nonlinearity is defined as the deviation of a code from a  
precise analog input voltage. Maximum specifications are limited by the  
LSB step size and the single shot measurement. Typical specifications are  
measured from 1/4, 1/2, 3/4 areas of the quantization band.  
Note 5: Guaranteed by design and not subject to test.  
4222f  
5

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