Datasheet > SY75572L

SY75572L

更新时间： 2023-12-06 20:11:46

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
20页	3518K
描述
The SY75572L is a high-speed, fully differential 1:2 clock fanout buffer with a 2:1 input MUX opti

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SY75572L 数据手册

SY75572L

267 MHz 1:2 3.3V HCSL/LVDS Fanout Buffer

Features

General Description

• Two Differential Pairs of LVDS or HCSL Outputs

The SY75572L is a high-speed, fully differential 1:2

clock fanout buffer with a 2:1 input MUX optimized to

provide two identical output copies with 137 fs phase

jitter and a maximum of 50 ps output-to-output skew.

Designed to be used with PCI Express applications, the

SY75572L accepts and outputs HCSL or LVDS logic

levels.

• Two Pairs of Differential Inputs Accept LVDS or

HCSL Logic Levels

• 267 MHz Maximum Frequency

• Ultra-Low Phase Jitter:

- 137 fs_RMS, 200 MHz (12 kHz - 20 MHz)

- 153 fs_RMS, 156.25 MHz (12 kHz - 20 MHz)

- 212 fs_RMS, 100 MHz (12 kHz - 20 MHz)

• <2 ps Total Jitter (peak-to-peak), 200 MHz

The SY75572L operates from a 3.3V ±5% power

supply and is guaranteed over the full industrial

temperature range (–40°C to +85°C). It is available in a

16-pin QFN lead-free package.

(BER = 10^–12

)

• 50 ps Output-to-Output Skew

The SY75572L is part of Microchip’s high-speed,

ultra-low jitter, PrecisionEdge™ product line. The

SY75572L supports PCIe Gen1-Gen4 requirements.

• 3.3V ±5% Power Supply Operation

• –40°C to +85°C Operating Temperature

• Available in 16-pin (3 mm × 3 mm) QFN

Lead-Free Package

Package Type

Applications

SY75572L

• Blade Servers

16-Pin QFN

• Desktop Servers

• Workstations

• Storage Area Networks

• IP Routers and Switches

• Telecom and Datacom

• High Performance Computing

16 15 14 13

/IN1

/Q0

PDB

GND

IN2

VDD

/IN2

 2022 - 2023 Microchip Technology Inc. and its subsidiaries

DS20006669B-page 1

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