ST20-GP1
GPS PROCESSOR
ENGINEERING DATA
FEATURES
■ Application specific features
• 12 channel GPS correlation DSP hardware
and ST20 CPU (for control and position calu-
culations) on one chip
GPS
radio
• no TCXO required
• RTCA-SC159 / WAAS / EGNOS supported
ST20-GP1
■ GPS performance
• accuracy
- stand alone
with SA on <100m, SA off <30m
- differential <1m
- surveying <1cm
• time to first fix
- autonomous start 90s
- cold start 45s
12 channel GPS
hardware DSP
ST20
CPU
- warm start 7s
Low
power
controller
Interrupt
controller
- obscuration 1s
■ 32-bit ST20 CPU
• 16/33 MHz processor clock
• 25 MIPS at 33 MHz
Real time
clock/calendar
Serial
• fast integer/bit operations
■ 4 Kbytes on-chip SRAM
• 130 Mbytes/s maximum bandwidth
■ Programmable memory interface
• 4 separately configurable regions
• 8/16-bits wide
• support for mixed memory
• 2 cycle external access
■ Serial communications
• Programmable UART (ASC)
• OS-Link
communications
2 UART (ASC)
1 OS-Link
4K
SRAM
.
.
.
Parallel
input/output
6
8
Programmable
memory
.
.
.
Byte-wide
parallel port
interface
■ Vectored interrupt subsystem
• 2 dedicated interrupt pins
• 5 levels of interrupt
■ Power management
ROM/
FLASH
RAM
• low power operation
• power down modes
■ Professional toolset support
• ANSI C compiler and libraries
• INQUEST advanced debugging tools
■ Technology
• Static clocked 50 MHz design
• 3.3 V, sub micron technology
■ 100 pin PQFP package
APPLICATIONS
■ Global Positioning System (GPS) receivers
■ Car navigation systems
■ Fleet management systems
■ Time reference for telecom systems
October 1996
1/116
42 1672 02
The information in this datasheet is subject to change