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SST406NL-E3

更新时间： 2024-02-04 08:43:19
品牌 Logo 应用领域
威世 - VISHAY 开关光电二极管晶体管
页数 文件大小 规格书
6页 81K
描述
Small Signal Field-Effect Transistor, 2-Element, N-Channel, Silicon, Junction FET, LEAD FREE, SOIC-8

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SST406NL-E3 技术参数

生命周期：Obsolete零件包装代码：SOT
包装说明：SMALL OUTLINE, R-PDSO-G8针数：8
Reach Compliance Code：unknown风险等级：5.63
其他特性：LOW NOISE配置：SEPARATE, 2 ELEMENTS
FET 技术：JUNCTION最大反馈电容 (Crss)：3 pF
JESD-30 代码：R-PDSO-G8元件数量：2
端子数量：8工作模式：DEPLETION MODE
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE极性/信道类型：N-CHANNEL
认证状态：Not Qualified表面贴装：YES
端子形式：GULL WING端子位置：DUAL
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

SST406NL-E3 数据手册

 浏览型号SST406NL-E3的Datasheet PDF文件第2页浏览型号SST406NL-E3的Datasheet PDF文件第3页浏览型号SST406NL-E3的Datasheet PDF文件第4页浏览型号SST406NL-E3的Datasheet PDF文件第5页浏览型号SST406NL-E3的Datasheet PDF文件第6页 
SST/U401NL Series  
New Product  
Vishay Siliconix  
Monolithic N-Channel JFET Duals  
SST404NL  
SST406NL  
U401NL  
U404NL  
U406NL  
PRODUCT SUMMARY  
Part Number  
VGS(off) (V)  
V(BR)GSS Min (V)  
gfs Min (mS)  
IG Typ (pA)  
ꢀ VGS1 - VGS2ꢀ Max (mV)  
U401NL  
-0.5 to -2.5  
-0.5 to -2.5  
-0.5 to -2.5  
-40  
-40  
-40  
1
1
1
-2  
-2  
-2  
5
SST/U404NL  
SST/U406NL  
15  
40  
FEATURES  
BENEFITS  
APPLICATIONS  
D Anti Latchup Capability  
D Monolithic Design  
D High Slew Rate  
D External Substrate Bias—Avoids Latchup  
D Tight Differential Match vs. Current  
D Improved Op Amp Speed, Settling Time Accuracy  
D Minimum Input Error/Trimming Requirement  
D Insignificant Signal Loss/Error Voltage  
D High System Sensitivity  
D Wideband Differential Amps  
D High-Speed,Temp-Compensated,  
Single-Ended Input Amps  
D High-Speed Comparators  
D Low Offset/Drift Voltage  
D Low Gate Leakage: 2 pA  
D Low Noise  
D Impedance Converters  
D High CMRR: 102 dB  
D Minimum Error with Large Input Signal  
DESCRIPTION  
The SST/U401NL series of high-performance monolithic dual  
JFETs features extremely low noise, tight offset voltage and  
low drift over temperature specifications, and is targeted for  
use in a wide range of precision instrumentation applications.  
This series has a wide selection of offset and drift  
specifications with the U401NL featuring a 5-mV offset and  
10-mV/_C drift.  
numbers enable the substrate to be connected to a positive  
polarity, external bias (VDD) to avoid latchup.  
The U series, hermetically sealed TO-78 package is  
available with full military processing. The SST series SO-8  
package provides ease of manufacturing, and the  
symmetrical pinout prevents improper orientation. The SO-8  
package is available with tape-and-reel options for  
compatibility with automatic assembly methods.  
Pins 4 and 8 of the SST series, and pin 4 of the U series part  
TO-78  
Narrow Body SOIC  
S
G
2
1
1
3
7
5
S
D
G
SUBSTRATE  
1
2
3
4
8
7
6
5
1
1
1
G
2
D
1
D
2
2
6
D
2
SUBSTRATE  
S
2
G
1
S
2
4
CASE, SUBSTRATE  
Top View  
Marking Codes:  
Top View  
U401NL  
U404NL  
U406NL  
SST404NL - 404NL  
SST406NL - 406NL  
ABSOLUTE MAXIMUM RATINGS  
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 V  
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA  
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C  
a
Power Dissipation :  
Per Side . . . . . . . . . . . . . . . . . . . . . . . . 300 mW  
b
Total . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW  
1
Lead Temperature ( / ” from case for 10 sec.) . . . . . . . . . . . . . . . . . . . 300_C  
16  
Notes  
Storage Temperature :  
U Prefix . . . . . . . . . . . . . . . . . . . . . -65 to 200_C  
a. Derate 2.4 mW/_C above 25_C  
b. Derate 4 mW/_C above 25_C  
SST Prefix . . . . . . . . . . . . . . . . . . . -55 to 150_C  
For applications information see AN106.  
Document Number: 72055  
S-22448—Rev. A, 17-Feb-03  
www.vishay.com  
7-1  
123456

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