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SPT9101SIS PDF预览

SPT9101SIS

更新时间： 2024-02-10 16:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 采样保持电路放大器放大器电路光电二极管
页数 文件大小 规格书
8页 58K
描述
125 MSPS SAMPLE-AND-HOLD AMPLIFIER

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SPT9101SIS 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：SOIC-20Reach Compliance Code：unknown
风险等级：5.8Is Samacsys：N
最长采集时间：0.016 µs标称采集时间：0.011 µs
放大器类型：SAMPLE AND HOLD CIRCUIT最大模拟输入电压：5 V
最小模拟输入电压：-5 V最大下降率：40000 V/s
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
负供电电压上限：-6 V标称负供电电压 (Vsup)：-5.2 V
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：5,-5.2 V
认证状态：Not Qualified采样并保持/跟踪并保持：SAMPLE
子类别：Sample and Hold Circuit最大压摆率：65 mA
供电电压上限：6 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BIPOLAR
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUALBase Number Matches：1

SPT9101SIS 数据手册

 浏览型号SPT9101SIS的Datasheet PDF文件第2页浏览型号SPT9101SIS的Datasheet PDF文件第3页浏览型号SPT9101SIS的Datasheet PDF文件第4页浏览型号SPT9101SIS的Datasheet PDF文件第6页浏览型号SPT9101SIS的Datasheet PDF文件第7页浏览型号SPT9101SIS的Datasheet PDF文件第8页 
Figure 2 - Typical Interface Circuit  
+
2.2 µF  
2.2 µF  
+
NOTES:  
-A5.2  
+A5  
1) V = Threshold voltage:  
t
a) For TTL or CMOS Clock input  
+A5  
12 13 17 18  
4
5
8
9
1k  
3k  
V
t
b) For ECL Clock input  
15  
18  
V
V
V
IN  
SPT9101  
V
OUT  
OUT  
IN  
-A5.2  
3k  
1k  
V
t
RTN  
1,2  
CLK NCLK  
10 11  
GND  
2) Unless otherwise specified, all capacitors  
are 0.01 or 0.1 µF, surface mount.  
6,7,16  
3) X = Termination (if required).  
330  
330  
-A5.2  
-A5.2  
4) CLKIN  
a) TTL/CMOS  
220  
CLKIN  
96850  
220  
2
R
8
R
3
4
V
CC  
11  
12  
IN+  
V
X
CLK IN  
EE  
SPT, HCMP96850  
GND  
V
IN-  
LE  
b) ECL: Direct Input  
t
1,16  
6
CLOCK DRIVER CIRCUIT (CLK, NCLK PINS)  
THEORY OF OPERATION  
Fairchild highly recommends that a differential ECL clock be  
used to drive the SPT9101. Both the 10KH and 100KH family  
of ECL logic can be used. The typical interface diagram,  
figure 2, shows the use of a SPT HCMP96850 high-speed  
comparator. The comparator has a typical propagation delay  
of 2.4 ns, very low offset of 3 mV, and a minimum tracking  
bandwidth of 300 MHz. The comparator shown has been set  
up in a feedthrough operation mode with latch enable con-  
nected to a logic high.  
The SPT9101 is a monolithic 125 MSPS track and hold  
amplifier built on a very high-speed complementary bipolar  
process.ItispinandfunctionallycompatiblewiththeAD9101.  
Itisatwostagedesignwithasamplerdrivingaholdcapacitor  
followed by a noninverting output buffer amplifier with gain of  
4. The first stage sampler is based on a current amplifier in  
noninverting gain of one configuration with inverting input  
connectedtotheoutput.Theholdswitchisintegratedintothis  
closed-loop first stage amplifier.  
The threshold voltage (V ) can be set using a resistor divider  
t
The output buffer amplifier is in a noninverting gain of 4  
configuration with inverting input connected to a resistor  
dividerdrivenfromtheoutput.Thenoninvertinginputfromthe  
hold capacitor employs input bias current cancellation which  
resultsinexcellentdrooprateperformance. Thesamplerand  
amplifier stages both employ complementary current ampli-  
fiers for high-speed, low-distortion performance.  
as shown in note 1 of figure 2. The configuration shown in  
note 1a is for a TTL/CMOS clock input and the configuration  
shown in note 1b is for an ECL clock input. The differential  
output of the comparator is directly fed to the SPT9101 clock  
input. The comparator can also be driven with a sinewave  
input, with the threshold voltage (V ) adjusted to produce the  
t
desired track/hold duty cycle ratio.  
Note 4a shows the resistor divider configuration for a TTL/  
CMOS clock input. If an ECL clock is used it can be directly  
fed into the comparator.  
TYPICAL INTERFACE CIRCUIT  
BOOTSTRAP CAPACITOR  
The SPT9101 does not require the bootstrap capacitor that is  
required on the AD9101 between pins 3 and 19. Because  
pins 3 and 19 are No Connects on the SPT9101, it will work  
well in existing AD9101 sockets.  
OUTPUT LEVEL SHIFTING (RTN PIN)  
The RTN pin is tied to the output buffer amplifier internal  
feedback resistor network as shown in the block diagram.  
Normallythispinistiedtogroundfora4xgainoutputamplifier  
configuration. However, this pin may be configured in other  
ways as long as certain guidelines are met.  
SPT9101  
5
12/30/99  
12345678

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