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SN74ABT377APWRG4 PDF预览

SN74ABT377APWRG4

更新时间: 2024-02-28 03:46:23
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件
页数 文件大小 规格书
21页 926K
描述
ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, TSSOP-20

SN74ABT377APWRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.43其他特性:WITH HOLD MODE
系列:ABTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:150000000 Hz
最大I(ol):0.064 A湿度敏感等级:1
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):30 mA传播延迟(tpd):7.3 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:150 MHzBase Number Matches:1

SN74ABT377APWRG4 数据手册

 浏览型号SN74ABT377APWRG4的Datasheet PDF文件第2页浏览型号SN74ABT377APWRG4的Datasheet PDF文件第3页浏览型号SN74ABT377APWRG4的Datasheet PDF文件第4页浏览型号SN74ABT377APWRG4的Datasheet PDF文件第5页浏览型号SN74ABT377APWRG4的Datasheet PDF文件第6页浏览型号SN74ABT377APWRG4的Datasheet PDF文件第7页 
SN54ABT377, SN74ABT377A  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLOCK ENABLE  
SCBS156E – FEBRUARY 1991 – REVISED JANUARY 1997  
SN54ABT377 . . . J OR W PACKAGE  
SN74ABT377A . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
CLKEN  
1Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
Typical V  
(Output Ground Bounce) < 1 V  
8Q  
8D  
7D  
OLP  
at V  
= 5 V, T = 25°C  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
GND  
CC  
A
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
16 7Q  
15 6Q  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
14  
13  
12  
11  
6D  
5D  
5Q  
CLK  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Plastic (N) and Ceramic (J) DIPs, and  
Ceramic Flat (W) Package  
SN54ABT377 . . . FK PACKAGE  
(TOP VIEW)  
description  
These 8-bit positive-edge-triggered D-type  
flip-flops with a clock (CLK) input are particularly  
suitable for implementing buffer and storage  
registers, shift registers, and pattern generators.  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
Data (D) input information that meets the setup  
time requirements is transferred to the Q outputs  
on the positive-going edge of the clock pulse if the  
common clock-enable (CLKEN) input is low.  
Clock triggering occurs at a particular voltage  
level and is not directly related to the transition  
time of the positive-going pulse. When the  
buffered clock (CLK) input is at either the high or  
low level, the D-input signal has no effect at the  
output. The circuits are designed to prevent false  
clocking by transitions at CLKEN.  
14 6D  
9 10 11 12 13  
The SN54ABT377 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ABT377A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLKEN CLK  
D
X
H
L
H
L
X
Q
0
H
L
L
X
H or L  
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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