Datasheet > SMP18FRUZ-REEL7

SMP18FRUZ-REEL7

更新时间： 2024-01-18 15:26:00

品牌	Logo	应用领域
亚德诺 - ADI		放大器光电二极管
页数	文件大小	规格书
9页	311K
描述
Fast Acquisition Octal Sample-and-Hold with Multiplexed Input

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技术参数
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SMP18FRUZ-REEL7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	5.44
标称采集时间：	3.5 µs	放大器类型：	SAMPLE AND HOLD CIRCUIT
最大模拟输入电压：	3 V	最小模拟输入电压：	-3 V
最大下降率：	0.04 V/s	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	5 mm
湿度敏感等级：	1	负供电电压上限：	-8.5 V
标称负供电电压 (Vsup)：	-5 V	功能数量：	8
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	1.2 mm	子类别：	Sample and Hold Circuit
最大压摆率：	9.5 mA	供电电压上限：	8.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	4.4 mm
Base Number Matches：	1

SMP18FRUZ-REEL7 数据手册

SMP18

+15V

1kΩ

2kΩ

10µF

1µF

10Ω

SMP18

10kΩ 10kΩ 10kΩ 10kΩ

Burn-in Circuit

POWER SUPPLY SEQUENCING

APPLICATIONS INFORMATION

V_DDshould be applied to the SMP18 before the logic input sig-

nals. The SMP18 has been designed to be immune to latchup,

but standard precautions should still be taken.

The SMP18, a multiplexed octal S/H, minimizes board space

in systems requiring cycled calibration or an array of control

voltages. When used in conjunction with a low cost 16-bit D/A,

the SMP18 can easily be integrated into microprocessor based

systems. Since the SMP18 features break-before-make switching

and an internal decoder, no external logic is required. The

SMP18 has an internally regulated TTL supply so that

TTL/CMOS compatibility is maintained over the full supply

range. See Figure 1 for channel decode address information.

OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15)

The buffer offset specification is 10 mV; this is less than 1/2

LSB of an 8-bit DAC with 10 V full scale. The hold step (mag-

nitude of step caused in the output voltage when switching from

sample-to-hold mode, also referred to as the pedestal error or

sample-to-hold offset) is about 4 mV with little variation over

the full output voltage range. The droop rate of a held channel

is 2 mV/s typical and 40 mV/s maximum.

POWER SUPPLIES

The SMP18 is capable of operating with either single or dual

supplies over a voltage range of 7 to 15 volts. Based on the sup-

ply voltages chosen, V_DDand V_SSestablish the output voltage

range, which is:

The buffers are designed to drive loads connected to ground.

The outputs can source more than 20 mA over the full voltage

range but have limited current sinking capability near V_SS. In

split supply operation, symmetrical output swings can be ob-

tained by restricting the output range to 2 V from either supply.

(V_SS+ 0.06 V) ≤ V_OUT≤ (V_DD– 2 V)

Note that several specifications, including acquisition time, off-

set and output voltage compliance, will degrade for supply volt-

ages of less than 7 V.

On-chip SMP18 buffers eliminate potential stability problems

associated with external buffers; outputs are stable with capaci-

tive loads up to 500 pF. However, since the SMP18’s buffer

outputs are not short circuit protected, care should be taken to

avoid shorting any output to the supplies or ground.

If split supplies are used, the negative supply should be bypassed

with a 0.1 µF capacitor in parallel with a 10 µF to ground. The

internal hold capacitors are connected to this supply pin, and

any noise will appear at the outputs.

SIGNAL INPUT (Pin 3)

In single supply applications, it is extremely important that the

The signal input should be driven from a low impedance voltage

source such as the output of an op amp. The op amp should

have a high slew rate and fast settling time if the SMP18’s ac-

quisition time characteristics are to be maintained. As with all

CMOS devices, all input voltages should be kept within range of

the supply rails (V_SS≤ V_IN≤ V_DD) to avoid the possibility of

latchup. If single supply operation is desired, op amps such as

the OP183 or AD820 that have input and output voltage com-

pliances including ground, can be used to drive the inputs. Split

supplies, such as ±7.5 V, can be used with the SMP18.

_SS(negative supply) pin is connected to a clean ground. The

hold capacitors are internally tied to the V_SS(negative) rail. Any

ground noise or disturbance will directly couple to the output of

the sample-and-hold degrading the signal-to-noise performance.

The analog and digital ground traces on the circuit board should

be physically separated to reduce digital switching noise from

entering the analog circuitry.

–6–

REV. C

1...4 5 678 9

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