SM5921A
8-channel Lip Sync Delay
OVERVIEW
The SM5921A is an SDRAM controller LSI for audio applications. It stores 64-fs slot 3-wire serial format
audio data input at sampling frequency fs in SDRAM, and can access data at an arbitrary address to add a delay
to each channel data. It also has a direct mute function to mute the audio data.
FEATURES
Functions
PINOUT
(Top view)
ꢀ System clock input
64fs (fs = 32 to 192kHz) bit clock
ꢀ Sampling frequency: fs = 32 to 192kHz support
ꢀ Data input/output
3-wire serial, 8-channel PCM
64 clock/slot, word clock polarity inversion
ꢀ Direct mute function
ꢀ MCU interface: 3-wire serial
ꢀ Delay settings: sum of intrinsic delay and individ-
ual delay
49
32 VSS
31 DQM
30 CLKO
29 CKE
28 A9
VDD
DQ3 50
DQ2 51
52
53
54
DQ1
DQ0
27 A8
DQ15
DQ14 55
26 A7
56
57
A6
A5
DQ13
DQ12
25
24
DQ11 58
DQ10 59
DQ9 60
23 A4
• Intrinsic delay (common to all channels,
default = 0 samples, 16-sample units)
• Individual delay (independent for each channel,
default = 0 samples, 1-sample units)
Maximum delay values
22 DOD
21
20
19
18
17
DOC
DOB
DOA
TEST
VDD
DQ8 61
WPOLN 62
OEN 63
VSS 64
1365.3ms @ fs = 48kHz
682.7ms @ fs = 96kHz
341.3ms @ fs = 192kHz
ꢀ Address shift function: ×1, ×2, ×4 support
Delay time can be multiplied between ×1, ×2, or
×4 times without changing the delay set value.
ꢀ SDRAM interface: 16M/64M/128M (×16 devices
supported)
PACKAGE DIMENSIONS
(Unit: mm)
Weight: 0.35g
ꢀ Package: 64-pin QFP
Structure
12 0ꢀ4
10 0ꢀ1
ꢀ Silicon-gate CMOS
Applications
ꢀ Audio delay for multi-channel PCM signals
ORDERING INFORMATION
Device
Package
0 to 10
SM5921AF
64-pin QFP
0ꢀ5
S
0ꢀ08 S
+ 0ꢀ09
0ꢀ18 − 0ꢀ05
Note. Dimensions without tolerance are reference values.
SEIKO NPC CORPORATION —1