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SC1112STRT

更新时间： 2024-01-09 00:00:34
品牌 Logo 应用领域
商升特 - SEMTECH 稳压器控制器
页数 文件大小 规格书
23页 354K
描述
Triple Low Dropout Regulator Controllers

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SC1112STRT 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-16针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.7
Is Samacsys：N其他特性：ALSO CONTAINS A CHARGE PUMP
模拟集成电路 - 其他类型：DUAL SWITCHING CONTROLLER最大输入电压：5.25 V
最小输入电压：4.75 V标称输入电压：5 V
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：5 mm功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Power Management Circuits最大供电电流 (Isup)：12 mA
标称供电电压 (Vsup)：5 V表面贴装：YES
切换器配置：PUSH-PULL温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

SC1112STRT 数据手册

 浏览型号SC1112STRT的Datasheet PDF文件第1页浏览型号SC1112STRT的Datasheet PDF文件第2页浏览型号SC1112STRT的Datasheet PDF文件第4页浏览型号SC1112STRT的Datasheet PDF文件第5页浏览型号SC1112STRT的Datasheet PDF文件第6页浏览型号SC1112STRT的Datasheet PDF文件第7页 
SC1112  
POWER MANAGEMENT  
Electrical Characteristics (Cont.)  
Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; TA = 25°C  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Units  
Linear Sections (Cont.)  
Output Voltage VTT  
(SC1112A)  
VTT1.2  
IO = 0 to 2A, VTTSEL = LOW  
IO = 0 to 2A, VTTSEL = LOW  
1.176  
1.225  
1.200  
1.250  
1.224  
1.275  
V
(SC1112)  
VTT1.25  
VTT1.5  
AGP1.5  
AGP3.3  
ADJ  
IO = 0 to 2A, VTTSEL = HIGH  
IO = 0 to 2A, AGPSEL = LOW  
IO = 0 to 2A, AGPSEL = HIGH  
IO = 0 to 2A  
1.470  
1.470  
3.234  
-2%  
1.500  
1.500  
1.530  
1.530  
V
V
Output Voltage AGP  
Output Voltage ADJ  
3.300  
V
1.2*(1+RA/RB)  
120  
+2%  
140  
V
VTTSEN Bias Current  
(SC1112)  
IbiasVTTSEN  
90  
µA  
VTTSEN Bias Current  
(SC1112A)  
IbiasVTTSEN  
1
5
µA  
AGPSEN Bias Current  
ADJSEN Bias Current  
VTT Gate Current  
IbiasAGPSEN  
IbiasADJSEN  
110  
150  
1
170  
5
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
%
IsourceVTTgate 5VSTBY = 4.75V, Vgate = 3.0V  
500  
500  
500  
500  
500  
500  
0.3  
IsinkVTTgate  
AGP Gate Current  
ADJ Gate Current  
IsourceAGPgate 5VSTBY = 4.75V, Vgate = 3.0V  
IsinkAGPgate  
IsourceADJgate 5VSTBY = 4.75V, Vgate = 3.0V  
IsinkADJgate  
Load Regulation  
Line Regulation  
LOADREG  
LINEREG  
VTTIN = 3.30V, IO = 0 to 2A  
VTTIN = 3.13V to 3.47V,  
Io = 2A  
0.3  
%
Gain (AOL)(2)  
GAINLDO  
LDOS Output to GATE  
50  
dB  
Notes:  
(1) All electrical characteristics are for the application circuit on page 19.  
(2) Guaranteed by design  
(3) Tracking Difference is defined as the delta between 3.3V Vin and the VTT, AGP, ADJ output voltages during the linear ramp up until  
regulation is achieved. The Tracking Voltage difference might vary depending on MOSFETs Rdson, and Load Conditions.  
(4) During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTINTH (1.5V). During the glitch  
timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit  
protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip  
threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input  
voltage or the 5VSTBY is cycled.  
(5) PWRGD pin is kept low during the power up, until the VTT output has reached its PGtd1.2 or PGtd1.5 level. At that time the PWRGD  
source current IPG (20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the  
capacitor is charged above the PGDelay_TH (1.5V), the PWRGD pin is released from ground.  
www.semtech.com  
2006 Semtech Corp.  
3
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