Datasheet > SC1112_06

SC1112_06

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
商升特 - SEMTECH		稳压器控制器
页数	文件大小	规格书
23页	354K
描述
Triple Low Dropout Regulator Controllers

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SC1112_06 数据手册

SC1112

POWER MANAGEMENT

Electrical Characteristics (Cont.)

Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; T_A= 25°C

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Linear Sections (Cont.)

Output Voltage VTT

(SC1112A)

VTT_1.2

I_O= 0 to 2A, VTTSEL = LOW

1.176

1.225

1.200

1.250

1.224

1.275

(SC1112)

VTT_1.25

VTT_1.5

AGP_1.5

AGP_3.3

ADJ

I_O= 0 to 2A, VTTSEL = HIGH

I_O= 0 to 2A, AGPSEL = LOW

I_O= 0 to 2A, AGPSEL = HIGH

I_O= 0 to 2A

1.470

3.234

-2%

1.500

1.530

Output Voltage AGP

Output Voltage ADJ

3.300

1.2*(1+RA/RB)

120

+2%

140

VTTSEN Bias Current

(SC1112)

Ibias_VTTSEN

µA

VTTSEN Bias Current

(SC1112A)

Ibias_VTTSEN

µA

AGPSEN Bias Current

ADJSEN Bias Current

VTT Gate Current

Ibias_AGPSEN

Ibias_ADJSEN

110

150

170

µA

Isource_VTTgate5VSTBY = 4.75V, Vgate = 3.0V

500

0.3

Isink_VTTgate

AGP Gate Current

ADJ Gate Current

Isource_AGPgate5VSTBY = 4.75V, Vgate = 3.0V

Isink_AGPgate

Isource_ADJgate5VSTBY = 4.75V, Vgate = 3.0V

Isink_ADJgate

Load Regulation

Line Regulation

LOAD_REG

LINE_REG

VTTIN = 3.30V, I_O= 0 to 2A

VTTIN = 3.13V to 3.47V,

Io = 2A

0.3

Gain (AOL)⁽²⁾

GAIN_LDO

LDOS Output to GATE

Notes:

(1) All electrical characteristics are for the application circuit on page 19.

(2) Guaranteed by design

(3) Tracking Difference is defined as the delta between 3.3V Vin and the VTT, AGP, ADJ output voltages during the linear ramp up until

regulation is achieved. The Tracking Voltage difference might vary depending on MOSFETs Rdson, and Load Conditions.

(4) During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTIN_TH(1.5V). During the glitch

timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit

protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip

threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input

voltage or the 5VSTBY is cycled.

(5) PWRGD pin is kept low during the power up, until the VTT output has reached its PG_td1.2or PG_td1.5level. At that time the PWRGD

source current I_PG(20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the

capacitor is charged above the PG_{Delay_TH}(1.5V), the PWRGD pin is released from ground.

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