Datasheet > S79FL512SDSMFVG01

S79FL512SDSMFVG01

更新时间： 2023-12-06 20:03:14

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S79FL512SDSMFVG01 数据手册

256 Mb (32 MB) / 512 Mb (64MB) FL-S Flash

SPI Dual-Quad, 3.0 V

Overview

1.1

General description

The S79FL256S/S79FL512S devices are flash non-volatile memory products using:

• MIRRORBIT™ technology - that stores two data bits in each memory array transistor

• Eclipse architecture - that dramatically improves program and erase performance

• 65-nm process lithography

The S79FL256S/S79FL512S devices connect two quad I/O SPI devices with a single CS# resulting in an eight bit

I/O data path. This byte I/O interface is called dual-quad I/O.

These devices connect to a host system via an SPI. Traditional SPI single bit serial input and output (IO1 and IO5)

is supported as well as four-bit (Quad I/O or QIO) serial commands. This multiple width interface is called SPI

multi-I/O or MIO. In addition, these two devices add support for DDR read commands for QIO that transfers

address and read data on both edges of the clock.

The Eclipse architecture features a page programming buffer that allows up to 256 words (512 bytes) or

512 words (1024 bytes) to be programmed in one operation, resulting in significantly faster effective

programming (up to 2 MB/s or 3 MB/s respectively) and erase (up to 1 MB/s) than prior generation SPI program

or erase algorithms.

Executing code directly from flash memory is often called eXecute-in-Place (XIP). By using the S79FL-S devices at

the higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match

or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count

dramatically.

The S79FL-S products offer high density coupled with the fastest read and write performance required by a

variety of embedded applications. They are ideal for code shadowing, XIP, and data storage.

Datasheet

6 of 134

002-00518 Rev. *F

2022-05-27

1...3 4 567 8 9...134

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