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S3922-128Q PDF预览

S3922-128Q

更新时间: 2024-01-21 00:07:27
品牌 Logo 应用领域
HAMAMATSU 传感器换能器
页数 文件大小 规格书
6页 224K
描述
NMOS Sensor, Rectangular, Through Hole Mount, DIP-22

S3922-128Q 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:unknown风险等级:5.66
阵列类型:LINEAR主体宽度:10.16 mm
主体高度:3 mm主体长度或直径:31.75 mm
外壳:QUARTZ GLASS安装特点:THROUGH HOLE MOUNT
最高工作温度:65 °C最低工作温度:-40 °C
输出类型:ANALOG VOLTAGE封装形状/形式:RECTANGULAR
传感器/换能器类型:IMAGE SENSOR,NMOS最大供电电压:10 V
最小供电电压:4.5 V表面贴装:NO
端接类型:SOLDERBase Number Matches:1

S3922-128Q 数据手册

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NMOS linear image sensor S3922/S3923 series  
Terminal  
φ1, φ2  
Input or output  
Input  
(CMOS logic compatible)  
Description  
Pulses for operating the MOS shift register. The video data rate is equal to  
the clock pulse frequency since the video output signal is obtained  
synchronously with the rise of φ2 pulse.  
Pulse for starting the MOS shift register operation. The time interval between  
Input  
(CMOS logic compatible) start pulses is equal to the signal accumulation time.  
φst  
Vss  
Vscg  
-
Connected to the anode of each photodiode. This should be grounded.  
Used for restricting blooming. This should be grounded.  
Input  
Input  
(CMOS logic compatible)  
Reset φ  
With Reset φ at high level, the video line is reset at the Reset V voltage.  
The Reset V terminal connects to each photodiode cathode via the video  
line when the address turns on. A positive voltage should be applied to the  
Reset V terminal to use each photodiode at a reverse bias. Setting the  
Reset V voltage to 2.5 V is recommended when the amplitude of φ1, φ2 and  
Reset φ is 5 V. Terminal pin 7 is used for both Reset V and Vscd.  
Used for restricting blooming. This should be biased at a voltage equal to  
“Reset V”.  
Reset V  
Input  
Vscd  
Input  
Low-impedance video output signal after internal current-voltage conversion.  
Negative-going output including DC offset.  
Active video  
Output  
This has the same structure as the active video, but is not connected to  
photodiodes, so only DC offset is output. Leave this terminal open when not  
used.  
Dummy video  
Output  
Vsub  
Vdd  
-
Connected to the silicon substrate. This should be grounded.  
Supply voltage to the internal impedance conversion circuit. A voltage equal  
to the amplitude of each clock should be applied to this terminal.  
This should be pulled up at 5 V by using a 10 kresistor. This is a negative  
going pulse that appears synchronously with the φ2 timing right after the last  
photodiode is addressed.  
Input  
Output  
(CMOS logic compatible)  
End of scan  
NC  
-
Should be grounded.  
Figure5 Spectralresponse(typicalexample)  
Figure 6 Output voltage vs. exposure  
(Typ. Reset V=2.5 V, Vdd=5.0 V, V =5.0 V, light source: 2856 K)  
(Typ. Reset V=2.5 V, Vdd=5.0 V, V =5.0 V, light source: 2856 K)  
SATURATION OUTPUT VOLTAGE  
(Ta=25 ˚C)  
101  
101  
100  
0.3  
SATURATION OUTPUT VOLTAGE  
100  
0.2  
0.1  
10-1  
10-2  
10-3  
10-4  
10-1  
10-2  
10-3  
10-4  
S3922-128Q  
S3922-256Q  
S3923-256Q  
S3923-512Q  
S3922-512Q  
S3923-1024Q  
SATURATION EXPOSURE  
SATURATION EXPOSURE  
0
100  
200  
10-5  
10-4  
10-3  
EXPOSURE (lx · s)  
10-2  
10-1  
100  
400  
800  
WAVELENGTH (nm)  
600  
10-5  
10-4  
10-3  
EXPOSURE (lx · s)  
10-2  
10-1  
1200  
1000  
KMPDB0149EA  
KMPDB0120EA  
KMPDB0121EA  
Construction of image sensor  
The NMOS image sensor consists of a scanning circuit made  
up of MOS transistors, a photodiode array, and a switching  
transistor array that addresses each photodiode, all integrated  
onto a monolithic silicon chip. Figure 1 shows the circuit of a  
NMOS linear image sensor.  
The MOS scanning circuit operates at low power consump-  
tion and generates a scanning pulse train by using a start  
pulse and 2-phase clock pulses in order to turn on each ad-  
dress sequentially. Each address switch is comprised of an  
NMOS transistor using the photodiode as the source, the  
video line as the drain and the scanning pulse input section  
as the gate.  
The photodiode array operates in charge integration mode  
so that the output is proportional to the amount of light expo-  
sure (light intensity × integration time).  
Each cell consists of an active photodiode and a dummy  
diode, which are respectively connected to the active video  
line and the dummy video line via a switching transistor. Each  
of the active photodiodes is also connected to the saturation  
control drain via the saturation control gate, so that the photo-  
diode blooming can be suppressed by grounding the satura-  
tion control gate. Applying a pulse signal to the saturation  
control gate triggers all reset. (See “Auxiliary functions”.)  

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