Datasheet
RMQSDA3636DGBA, RMQSDA3618DGBA
R10DS0243EJ0100
36-Mbit QDR™ II+ SRAM 4-word Burst
Rev. 1.00
May 25, 2015
Architecture (2.5 Cycle Read latency) with ODT
Description
The RMQSDA3636DGBA is a 1,048,576-word by 36-bit and the RMQSDA3618DGBA is a 2,097,152-word by 18-bit
synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor
memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are
controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are
suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit
configuration. These products are packaged in 165-pin plastic FBGA package.
Features
¢ Power Supply
ò
1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ
)
¢ Clock
ò
ò
ò
ò
Fast clock cycle time for high bandwidth
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
Clock-stop capability with µs restart
¢
I/O
ò
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR read and write operation
HSTL I/O
User programmable output impedance
PLL circuitry for wide output data valid window and future frequency scaling
Data valid pin (QVLD) to indicate valid data on the output
ò
ò
ò
ò
ò
¢ Function
ò
ò
ò
ò
Four-tick burst for reduced address frequency
Internally self-timed write control
Simple control logic for easy depth expansion
JTAG 1149.1 compatible test access port
¢ Package
ò
165 FBGA package (13 x 15 x 1.4 mm)
R10DS0243EJ0100 Rev. 1.00
May 25, 2015
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