Datasheet > RC19202

RC19202

更新时间： 2023-12-20 18:44:05

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
69页	1954K
描述
PCIe Gen6 2:2 Clock Multiplexer

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RC19202 数据手册

RC192xx Datasheet

Table 1. RC19216 Pin Descriptions (Cont.)

Type Description

Pin Number

Pin Name

Active low input for enabling output group D, or the clock pin for the Side-Band

Interface. The function of this pin is controlled by the SBI_EN or SBI_ENQ pin.

Refer to the Side-band Interface section and Table 5 for details.

I, SE,

PDT, PU

or PD

11 OEb_D_SBI_CLK

OE mode with internal pull-up:

0 = enable output, 1 = disable output.

Side-Band mode: SBI clock input with internal pull-down.

12 CLKb7

O, DIF Complementary clock output.

SMBus address bit. This is a tri-level input that works in conjunction with other

I, SE, PD, SADR pins, if present, to decode SMBus Addresses. See the SMBus Address

SADR_tri0

Selection (RC19208, RC19216) table and refer to the tri-level input thresholds in

the electrical tables.

VDDIN0

PWR

Power supply for clock input 0.

Power supply for analog circuitry.

11 VDDA

12 CLK7

O, DIF True clock output.

CLKIN1

I, DIF

True clock input.

No connect.

11 NC

No connect.

12 VDDCLK_0

PWR

I, DIF

Power supply for clock output bank 0.

Complementary clock input.

CLKINb1

SDATA

I/O, SE,

OD, PDT

Data pin for SMBus interface.

11 VDDCLK_1

12 LOSb

PWR

Power supply for clock output bank 1.

Output indicating Loss of Input Signal. This pin is an open drain output and requires

an external pull up resistor for proper functionality. A low output on this pin indicates

a loss of signal on the input clock.

O, OD,

PDT

I, SE,

PDT

SCLK

Clock pin of SMBus interface.

VDDIN1

PWR

Power supply for clock input 1.

No connect.

11 NC

12 CLKb8

O, DIF Complementary clock output.

VDDCLK_1

PWR

Power supply for clock output bank 1.

No connect.

Active low input for enabling output group E, or the data pin for the Side-Band

Interface. The function of this pin is controlled by the SBI_EN or SBI_ENQ pin.

Refer to the Side-band Interface section and Table 5 for details.

I, SE,

PDT, PU

or PD

OE mode with internal pull-up:

11 OEb_E_SBI_IN

0 = enable output, 1 = disable output.

Side-Band mode with internal pull-down:

SBI shift-register data input.

12 CLK8

CLK15

O, DIF True clock output.

R31DS0020EU0107 Rev.1.07

July 26, 2023

Page 7

1...4 5 678 9 10...69

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