Datasheet > R1Q3A4436RBG-33I

R1Q3A4436RBG-33I

更新时间： 2023-12-20 18:46:34

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
30页	953K
描述
144-Mbit QDR? II SRAM 4-word Burst

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R1Q3A4436RBG-33I 数据手册

Datasheet

R1Q3A4436RBG, R1Q3A4418RBG

R10DS0141EJ0101

Rev.1.01

144-Mbit QDR™ II SRAM

4-word Burst

Aug 01, 2014

Description

The R1Q3A4436RBG is a 4,194,304-word by 36-bit and the R1Q3A4418RBG is a 8,388,608-word by 18-bit

synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor

memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are

controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are

suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit

configuration. These products are packaged in 165-pin plastic FBGA package.

Features

Power Supply

1.8 V for core (V^DD), 1.4 V to VDD for I/O (VDD )

Clock

Fast clock cycle time for high bandwidth

Two input clocks (K and /K) for precise DDR timing at clock rising edges only

Two input clocks for output data (C and /C) to minimize clock skew and flight time mismatches

Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems

Clock-stop capability with μs restart

I/O

Separate independent read and write data ports with concurrent transactions

100% bus utilization DDR read and write operation

HSTL I/O

User programmable output impedance

PLL circuitry for wide output data valid window and future frequency scaling

Function

Four-tick burst for reduced address frequency

Internally self-timed write control

Simple control logic for easy depth expansion

JTAG 1149.1 compatible test access port

Package

165 FBGA package (15 x 17 x 1.4 mm)

R10DS0140EJ0101 Rev.1.01

Aug 01, 2014

Page 1 of 29

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