Datasheet > QDC10

QDC10

更新时间： 2022-12-17 02:53:08

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YAMAR		电池
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描述
Multiplex Data On Battery Power Lines

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QDC10 数据手册

QDC10 - Multiplex Data on Battery Power Lines

Res1 Res6

RxEnable RxData

Res2

~Reset

Vss

OscIn

OscOut

Vdd

DataIn

TxData

TxEnable

Res3

DataOut

ClockIn

Res5

Res4

QDC10

Figure 4.1 - Device Pin-out

4.1

Host interface

4.1.1

Host Interface Ports

Three lines control the operation of the Host interface. The QDC10 device receives and sends data in

bytes, MSB bit first.

ClockIn

Host

micro-

controller

QDC10

device

DataIn

DataOut

Figure 4.2 - Host Interface signals

4.1.1.1

ClockIn

Clock signal from the Host for the synchronous interface.

4.1.1.2

DataIn

Data input signal to the QDC10.

1) Transfer Data from Host to QDC10 during the falling edge of ClockIn signal.

2) When high, indicates to the QDC10 that Host is ready to send data. When low, Host is busy.

4.1.1.3

DataOut

Data out signal from the QDC10.

1) Transfers Data to Host on the rising edge of ClockIn. DataOut transitions on falling edge of ClockIn.

2) On the rise of DataOut signal the QDC10 indicates the Host that a data byte is ready to be transferred

to the Host (DataIn and ClockIn have to be low).

4.1.2

Data Transfers

Data transfers between Host and QDC10 should be performed by the Host in the highest speed allowed

by this data sheet to reduce the message delay between devices. During Data transfer, the QDC10

does not listen to the DC line. If during message transfer to/from Host, the Host does not send clock for

more than 65mS between two consecutive bytes, the QDC10 will abort its Data transfer task and return

to Receive (search for new message on the DC-BUS).

4.1.2.1

QDC10 to Host data transfer

Byte transfer starts after the QDC10 checks that DataIn is low, then raise its DataOut signal to interrupt

the Host. When ready, the Host raises its ClockIn and DataIn signals to indicate the QDC10 to continue

the byte transfer. The QDC10 sets its DataOut according to the bit to be sent and waits for the falling of

the ClockIn signal to update its DataOut. The Host has to sample the DataOut on the rising edge of the

ClockIn. This data transfer continues for 8 bits, then the QDC10 sets its DataOut signal to Low. If the

Host is ready to receive another byte, it lowers the DataIn signal.

Notice: 9 clocks are used for a byte transfer from QDC10 to Host

DS-QDC10 R1.5

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