Datasheet > PSD853F3VA-90MIT

PSD853F3VA-90MIT

更新时间： 2022-03-04 06:04:42

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
128页	1134K
描述
Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

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PSD853F3VA-90MIT 数据手册

PSD8XXFX

Flash in-system programmable (ISP)

peripherals for 8-bit MCUs, 5 V

Features

■ Flash in-system programmable (ISP)

peripheral for 8-bit MCUs

■ Dual bank Flash memories

PQFP52 (M)

– Up to 2 Mbit of primary Flash memory (8

uniform sectors, 32K x8)

– Up to 256 Kbit secondary Flash memory (4

uniform sectors)

– Concurrent operation: read from one

memory while erasing and writing the other

■ Up to 256 Kbit SRAM

■ 27 reconfigurable I/Oports

■ Enhanced JTAG serial port

PLCC52 (J)

■ PLD with macrocells

– Over 3000 gates of PLD: CPLD and DPLD

– CPLD with 16 output macrocells (OMCs)

and 24 input macrocells (IMCs)

– DPLD - user defined internal chip select

decoding

TQFP64 (U)

■ 27 individually configurable I/O port pins

■ Programmable power management

They can be used for the following functions:

– MCU I/Os

■ Packages are ECOPACK

– PLD I/Os

– Latched MCU address output

– Special function I/Os.

Table 1.

Device summary

Reference

Part number

– 16 of the I/O ports may be configured as

open-drain outputs.

PSD813F2

PSD813F4

PSD813F5

PSD833F2

PSD834F2

PSD853F2

PSD854F2

■ In-system programming (ISP) with JTAG

– Built-in JTAG compliant serial port allows

full-chip in-system programmability

– Efficient manufacturing allow easy product

testing and programming

PSD8XXFX

– Use low cost FlashLINK cable with PC

■ Page register

– Internal page register that can be used to

expand the microcontroller address space

by a factor of 256

May 2009

Doc ID 7833 Rev 7

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