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PPXS2005VMM80R PDF预览

PPXS2005VMM80R

更新时间: 2024-02-16 21:09:20
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 微控制器
页数 文件大小 规格书
30页 137K
描述
32-bit Power Architecture® Microcontrollers for Highly Reliable

PPXS2005VMM80R 数据手册

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Features  
2.1  
PXS20 Features  
Table 1 displays the PXS20 feature set.  
Table 1. PXS20 Family Feature Set  
Feature  
PXS20  
CPU  
Type  
2 × e200z4  
(in lock-step or decoupled operation)  
Architecture  
Harvard  
Execution speed  
DMIPS intrinsic performance  
SIMD (DSP + FPU)  
MMU  
0 – 120 MHz (+2% FM)  
> 240 MIPS  
Yes  
16 entry  
Instruction set PPC  
Instruction set VLE  
Instruction cache  
MPU-16 regions  
Yes  
Yes  
4 KB, EDC  
Yes, replicated module  
Yes  
Semaphore unit (SEMA4)  
Core bus  
Buses  
AHB, 32-bit address, 64-bit data  
32-bit address, 32-bit data  
Internal periphery bus  
Master × slave ports  
Crossbar  
Memory  
Lock Step Mode: 4 × 3  
Decoupled Parallel Mode: 6 × 3  
Code/data flash  
1 MB, ECC, RWW  
128 KB, ECC  
Static RAM (SRAM)  
Interrupt controller (INTC)  
Periodic Interrupt Timer (PIT)  
System timer module (STM)  
Software watchdog timer (SWT)  
eDMA  
Modules  
16 interrupt levels, replicated module  
1 × 4 channels  
1 × 4 channels, replicated module  
Yes, replicated module  
16 channels, replicated module  
1 × 64 message buffers, dual channel  
2 × 32 message buffers  
2
FlexRay  
CAN  
UART with DMA support  
Clock out  
Yes  
Fault control & collection unit (FCCU)  
Cross triggering unit (CTU)  
eTimer  
Yes  
Yes  
3 × 6 channels  
PWM  
2 Module 4 × (2 + 1) channels  
Analog-to-digital converter (ADC)  
2 × 12-bit ADC, 16 channels per ADC  
(3 internal, 4 shared and 9 external)  
PXS20 Product Brief, Rev. 1  
Freescale Semiconductor  
3

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