Datasheet > PPXS1010VLU64R

PPXS1010VLU64R

更新时间： 2024-01-31 21:03:09

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
26页	128K
描述
32-bit Power ArchitectureÂ® Microcontrollers for Entry Level Display Solutions

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数据手册

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PPXS1010VLU64R 数据手册

Features

— Display control unit

•

4 slave ports

— 1 flash port dedicated to the CPU

— Platform SRAM

— QuadSPI serial flash controller

— 1 slave port combining:

– Flash port dedicated to the Display Control Unit and eDMA module

– Graphics SRAM

– Peripheral bridge

•

32-bit internal address bus, 32-bit internal data bus

2.4.27 Enhanced Direct Memory Access (eDMA)

The eDMA module is a controller capable of performing complex data movements via 16 programmable

channels, with minimal intervention from the host processor. The hardware micro architecture includes a

DMA engine which performs source and destination address calculations, and the actual data movement

operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the

channels. This implementation is utilized to minimize the overall block size. The eDMA module provides

the following features:

•

16 channels support independent 8-, 16- or 32-bit single value or block transfers

Supports variable sized queues and circular queues

Source and destination address registers are independently configured to post-increment or remain

constant

•

Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request

Each DMA channel can optionally send an interrupt request to the CPU on completion of a single

value or block transfer

•

DMA transfers possible between system memories, QuadSPI, SPIs, I C, ADC, eMIOS and

General Purpose I/Os (GPIOs)

Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA

channel with up to a total of 64 potential request sources.

2.4.28

Memory Protection Unit (MPU)

The MPU features the following:

•

12 region descriptors for per-master protection

Start and end address defined with 32-byte granularity

Overlapping regions supported

Protection attributes can optionally include process ID

Protection offered for 3 concurrent read ports

Read and write attributes for all masters

Execute and supervisor/user mode attributes for processor masters

PXD10 Product Brief, Rev. 1

Freescale Semiconductor

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